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參數(shù)資料
| 型號(hào)： | MC12439FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | MC12439FNR2 |
4
MC12439
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
392
N[1:0] inputs will affect the FOUT output pair. To use the serial
port, the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 12 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation to
function. The Test register is loaded with the first three bits, the
N register with the next two and the M register with the final eight
bits of the data stream on the S_DATA input. For each register,
the most significant bit is loaded first (T2, N1 and M6). A pulse
on the S_LOAD pin after the shift register is fully loaded will
transfer the divide values into the counters. The HIGH to LOW
transition on the S_LOAD input will latch the new divide values
into the counters. Figure 2 illustrates the timing diagram for both
a parallel and a serial load of the MC12439 synthesizer.
M[6:0] and N[1:0] are normally specified once at power–up
through the parallel interface, and then possibly again through
the serial interface. This approach allows the application to
come up at one frequency and then change or fine–tune the
clock as the ability to control the serial interface becomes
available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
represents FOUT, the CMOS output may not be able to toggle
fast enough for some of the higher output frequencies. The T2,
T1 and T0 control bits are preset to ‘000’ when P_LOAD is LOW
so that the PECL FOUT outputs are as jitter–free as possible.
Any active signal on the TEST output pin will have detrimental
affects on the jitter of the PECL output pair. In normal
operations, jitter specifications are only guaranteed if the TEST
output is static. The serial configuration port can be used to
select one of the alternate functions for this pin.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MC12439 itself.
However the PLL bypass mode may be of interest at the board
level for functional debug. When T[2:0] is set to 110, the
MC12439 is placed in PLL bypass mode. In this mode, the
S_CLOCK input is fed directly into the M and N dividers. The N
divider drives the FOUT differential pair and the M counter drives
the TEST output pin. In this mode, the S_CLOCK input could be
used for low speed board level functional test or debug.
Bypassing the PLL and driving FOUT directly gives the user
more control on the test clocks sent through the clock tree.
Figure 3 shows the functional setup of the PLL bypass mode.
Because the S_CLOCK is a CMOS level, the input frequency
is limited to 250 MHz or less. This means the fastest the FOUT
pin can be toggled via the S_CLOCK is 250 MHz as the
minimum divide ratio of the N counter is 1. Note that the M
counter output on the TEST output will not be a 50% duty cycle
due to the way the divider is implemented.
T2
T1
T0
TEST (Pin 20)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT/2
FOUT
LOW
M COUNTER/2 in
PLL Bypass Mode
FOUT/4
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC1243F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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