參數(shù)資料
型號(hào)： MC13109A
廠(chǎng)商： Motorola, Inc.
英文描述： UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC
中文描述： 通用無(wú)繩電話(huà)子系統(tǒng)集成電路
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 1307K
代理商： MC13109A
MC13109A
23
MOTOROLA RF/IF DEVICE DATA
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Figure 27. Test Mode Description
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value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
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Counter Under Test or
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“Tx VCO”
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Test Modes
Test Mode Control latch bits enable independent testing of
internal counters and set AGC Gain Options. In test mode,
the “Tx VCO” input pin is multiplexed to the input of the
counter under test and the output of the counter under test is
multiplexed to the “Clk Out” output pin so that each counter
can be individually tested. Make sure test mode bits are set to
“0” for normal operation. Test mode operation is described in
Figure 27. During normal operation and when testing the Tx
Prescaler, the “Tx VCO” input can be a minimum of 200 mVpp
at 80 MHz and should be ac coupled. For other test modes,
input signals should be standard logic levels of 0 to 2.2 V and
a maximum frequency of 16 MHz.
Power–Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The MC13109A is initially placed
in the Rx mode with all mutes active and nothing disabled.
The reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output
frequency. The Tx and Rx latch registers are set for USA
Channel Frequency #21. Figure 28 shows the initial
power–up states for all latch registers.
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Register
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Count
15
14
13
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1
12
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11
10
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9
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–
1
0
0
1
1
Rx
7215
–
0
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1
0
0
0
1
0
1
1
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Ref
2048
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–
0
0
1
0
–
0
0
0
0
0
0
0
–
0
Gain
N/A
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–
–
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–
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–
1
1
0
0
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