參數(shù)資料
型號(hào)： MC13109AFB
廠商： MOTOROLA INC
元件分類(lèi)： 無(wú)繩電話(huà)/電話(huà)
英文描述： UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC
中文描述： TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP52
封裝： PLASTIC, QFP-52
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 1307K
代理商： MC13109AFB
MC13109A
15
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.6 V, TA = 25
°
C)
Characteristic
Unit
Max
Typ
Min
Symbol
Measure
Pin
Condition
PLL PIN INTERFACE
EN to Clk Setup Time
–
EN, Clk
tsuEC
tsuDC
th
trec
tw
tr, tf
200
–
–
ns
Data to Clk Setup Time
–
Data, Clk
100
–
–
ns
Hold Time
–
Data, Clk
90
–
–
ns
Recovery Time
–
EN, Clk
90
–
–
ns
Input Pulse Width
–
EN, Clk
100
–
–
ns
Input Rise and Fall Time
–
Data
Clk
EN
–
–
9.0
μ
s
MPU Interface
Power–Up Delay
90% of PLL Vref to
Data, Clk, EN
–
tpuMPU
–
100
–
μ
s
PLL LOOP
2nd LO Frequency
–
LO2 In
LO2 Out
fLO
–
–
12
MHz
“Tx VCO” Input Frequency
Vin = 200 mVpp
Tx VCO
ftxmax
–
–
80
MHz
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL’s and MPU serial interface are
normally powered by the internal voltage regulator at the “PLL
Vref” pin. The “PLL Vref” pin is the output of a voltage regulator
which is powered from the “V
CC
Audio” power supply pin.
Therefore, the maximum input and output levels for most PLL
I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the
regulated voltage at the “PLL Vref” pin. The ESD protection
diodes on these pins are also connected to “PLL Vref”.
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is V
CC
.
Figure 5 shows a simplified schematic of the PLL I/O pins.
Figure 5. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
In
I/O
VCC Audio
(2.0 to 5.5 V)
PLL Vref
(2.2 V)
VCC Audio
(2.0 to 5.5 V)
Clk Out Pin
Data, Clk, and EN Pins
LO2 In, LO2 Out,
Rx PD, Tx PD and
Tx VCO Pins
Out
2.0
μ
A
1.0 k
Microprocessor Serial Interface
The “Data”, “Clk”, and “EN” pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The “Data” and “Clk” pins are used to load
data into the shift register. Figure 6 shows “Data” and “Clk”
pin timing. Data is clocked on positive clock transitions.
Figure 6. Data and Clock Timing Requirement
Data,
Clk, EN
Data
Clk
tsuDC
tr
tf
50%
50%
th
10%
90%
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–Bit address is loaded
into the shift register and latched into the 8–Bit address latch
register. Then, up to 16–Bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 7 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
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