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參數(shù)資料
| 型號： | MC13109AFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 1307K |
| 代理商： | MC13109AFB |
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MC13109A
20
MOTOROLA RF/IF DEVICE DATA
“Clk Out” Divider Programming
The “Clk Out” pin is derived from the 2nd local oscillator and
can be used to drive a microprocessor, thereby reducing the
number of crystals required. Figure 19 shows the relationship
between the crystal frequency and the clock output for
different divider values. Figure 20 shows the “Clk Out” register
bit values.
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12.00 MHz
6.000 MHz
4.000 MHz
2.400 MHz
1.200 MHz
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Bit #1
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0
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Bit #2
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2
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Divider Value
0
0
1
3
1
0
5
1
1
10
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 10”. This
provides an MPU clock of about 1.0 MHz after initial
power–up. The reason for choosing this relatively low clock
frequency after intial power–up is that some microprocessors
that operate down to a 2.0 V power supply have a maximum
clock frequency of 1.0 MHz. After initial power–up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another is “smooth”
(i.e., there will be no narrow clock pulses to disturb the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13109A and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 k
resistor is included on–chip in–series with the “Clk Out” output
driver. A small capacitor can be connected to the “Clk Out” line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the “Clk Out” line.
Volume Control
The volume control can be programmed in 2.0 dB gain steps
from –14 dB to 16 dB. The power–up default value is 0 dB.
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Gain Control Register
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 22 and 23.
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Bit #3
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Bit #2
0
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0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
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Bit #1
0
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0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
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Figure 22. Gain Control Latch Bits
Bit #0
0
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1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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Control #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Amount
–14 dB
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–12 dB
–10 dB
–8.0 dB
–6.0 dB
–4.0 dB
–2.0 dB
0 dB
2.0 dB
4.0 dB
6.0 dB
8.0 dB
10 dB
12 dB
14 dB
16 dB
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0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MSB
LSB
5–Bit CD Threshold Control
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