參數(shù)資料
型號: MC13224V
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA99
封裝: 9.50 X 9.50 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, LGA-99
文件頁數(shù): 14/54頁
文件大?。?/td> 490K
代理商: MC13224V
MC1322x Technical Data, Rev. 1.3
Freescale Semiconductor
21
5.3
Timer (TMR) Module
The MC1322x provides a timer module (TMR) that contains four identical counter/timer groups. Each
group is capable of many variants of input capture, output compare and pulse-width modulation. The wide
range of operational modes is useful for many control and sensor applications.
Figure 7 shows a block diagram of an individual timer group.
Figure 7. Timer Group Block Diagram
Each 16-bit counter/timer group contains a prescaler, a counter, a load register, a hold register, a capture
register, two compare registers, and status and control registers.
Load Register — Provides the initialization value to the counter when the counter’s terminal value
has been reached
Hold Register — Captures the counter’s value when other counters are being read. This feature
supports the reading of cascaded counters
Capture Register — Enables an external signal to take a snap shot of the counter’s current value
COMP1 and COMP2 Registers — Provides the values to which the counter is compared. If a match
occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated
(if enabled), and the new compare value is loaded into the COMP1 or COMP2 registers from
CMPLD1 and CMPLD2 if enabled
The Prescaler provides different time bases useful for clocking the counter/timer
CMPLD1
COMP1
LOAD
HOLD
STATUS AND
CONTROL
CMPLD2
COMP2
COUNTER
Comparator
CAPTURE
M
U
X
Prescaler
M
U
X
Peripheral
Reference
Clock
Other
Counter
Reference
OFLAG
Output
External
MCU
DATA
BUS
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