參數(shù)資料
型號(hào)： MC13224VR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA99
封裝： 9.50 X 9.50 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, LGA-99
文件頁(yè)數(shù)： 41/54頁(yè)
文件大小： 490K
代理商： MC13224VR2
MC1322x Technical Data, Rev. 1.3
46
Freescale Semiconductor
Table 20. I2C Signal AC Specifications1
1 All values referred to V
IHmin and VILmax levels
Parameter
Symbol
Standard-Mode
Fast-Mode
Unit
Min
Max
Min
Max
SCL clock frequency (when source)
fSCL
0
100
0
150
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
tHD;STA
4.0
-
0.6
-
μs
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
μs
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
μs
Set-up time for a repeated START condition
tSU;STA
4.7
-
0.6
-
μs
Data hold time
tSHD;DAT
02
2 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
3.453
3 The maximum t
HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
μs
Data setup time
tSU:DAT
250
-
1004
4 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t
SU;DAT >= 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max
+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is
released.
-ns
Rise time for both SDA and SCL signals
tr
-
1000
20 +
0.1Cb
5
5 C
b = total capacitance of one bus line in pF. If mixed with Hs-mode devices, the faster fall-times are allowed.
300
ns
Fall time for both SDA and SCL signals
tf
-
300
20 +
0.1Cb
300
ns
Bus free time between a STOP and START condition
tBUF
4.7
-
1.3
-
μs
Capacitive load for each bus line
Cb
-
400
-
400
pF
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