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參數(shù)資料
| 型號： | MC141541P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Fixed-Point Digital Signal Processor 570-FCPGA -40 to 105 |
| 中文描述： | ON-SCREEN DISPLAY IC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC141541P |
MC141541
14
MOTOROLA
DESIGN CONSIDERATIONS
Distortion
Motorola’s MC141541P has a built–in PLL for multi–sys-
tem application. Pin 2 voltage is dc–based for the internal
VCO in the PLL. When the input frequency (HFLB) to Pin 5
increases, the VCO frequency will increase accordingly. This
forces the PLL to a higher locked frequency output. The fre-
quency should be equal to 320/480 x HFLB (depending on
resolution).This is the pixel dot clock.
Display distortion is caused by noise on Pin 2. Positive
noise increases the VCO frequency above normal. The cor-
responding scan line will be shorter accordingly. In contrast,
negative noise causes the scan line to be longer. The net re-
sult will be distortion on the display, especially on the right
hand side of the display window.
In order to have distortion–free display, the following rec-
ommendations should be considered:
Only analog part grounds (Pin 2 to Pin 4) can be con-
nected to Pin 1(VSS(A)). VSS and other grounds should be
connected to PCB common ground. The VSS(A) and VSS
grounds should be totally separated (i.e. VSS(A) is float-
ing). Refer to the Application Diagram for the ground con-
nections.
The dc supply path for Pin 9 (VDD) should be separated
from other switching devices.
The LC filter should be connected between Pin 9 and Pin
4. Refer to the values used in the Application Diagram.
Biasing and filter networks should be connected to Pin 2
and Pin 3. Refer to the recommended networks in the Ap-
plication Diagram.
Two small capacitors can be connected between Pins 2
and 3, and between Pins 3 and 4.
Jittering
Most display jittering is caused by HFLB jittering on Pin 5.
Care must be taken if the HFLB signal comes from the fly-
back transformer. A short path and shielded cable are rec-
ommended for a clean signal. A small capacitor can be
added between Pin 5 and Pin 16 to smooth the signal. Refer
to the value used in the Application Diagram.
Display Dancing
Most display dancing is caused by interference of the seri-
al bus. It can be avoided by adding series resistors to the se-
rial bus.
APPLICATION DIAGRAM
MPS2369
100
μ
H
0.1
μ
F
100
μ
F
ANALOG GROUND – FLOATING
100
100
100
240
240
240
VCC
VCC
1 k
1 k
1 k
0.1
μ
F
10
μ
F
9
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
0.01
μ
F
1 k
0.047
μ
F
33 pF
33 pF
100
100
100
VDD
VSS
R
G
B
FBKG
HTONE
VFLB
VSS(A)
VCO
RP
HFLB
SS
SDA(MOSI)
SCL(SCK)
VDD(A)
HFLB
2 k
VFLB
HTONE
FBKG
B
G
R
330 k
DIGITAL GROUND – COMMON GROUND
ANALOG GROUND
DIGITAL GROUND
EMOSD
IIC(SPI) BUS
330 pF
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