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參數(shù)資料
| 型號(hào)： | MC141541P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Fixed-Point Digital Signal Processor 570-FCPGA -40 to 105 |
| 中文描述： | ON-SCREEN DISPLAY IC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 361K |
| 代理商： | MC141541P |
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MC141541
8
MOTOROLA
REGISTERS
Display Register
CRADDR
0
1
2
3
4
5
6
7
CCS0
Bit 7 CCS0 — This bit defines a specific character color
out of the two preset colors. Color 1 is selected if this bit is
cleared, and Color 2 otherwise.
Bit 6–0 CRADDR — These seven bits address the 128
characters or symbols residing in the character ROM.
Row Control Registers
Coln 30
4
Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color
2 by R2, G2, and B2.
Bit 1 CHS — This bit determines the height of a display
symbol. When it is set, the symbol is displayed in double
height.
Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the
character is displayed in double width.
0
1
2
3
5
6
7
CWS
CHS
B2
G2
R2
B1
G1
R1
COLN 30
Coln 31
Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color
4 by R4, G4, and B4.
COLN 31
Window 1 Registers
Row 10 Coln 0
LSB
LSB
COLN 0
ROW 10
Row 10 Coln 1
MSB
WEN
CCS1
LSB
COLN 1
0
1
2
3
4
5
6
7
ROW 10
HPOL
Bit 2 WEN — This bit enables the background Window 1
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 1 with two extra color
selections, making a total of four selections for that row.
Bit 0 HPOL — This bit selects the polarity of the incoming
horizontal sync signal (HFLB) on Pin 5. If it is negative polar-
ity, clear this bit. Otherwise, set this bit to 1 to represent the
positive H sync signal. After power–on, this bit is cleared.
Row 10 Coln 2
COLN 2
ROW 10
Bits 2–0 R, G and B — These bits control the color of Win-
dow 1. Window 1 occupies Columns 0–2 of Row 10; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
Window 2 Registers
Row 10 Coln 3
Row 10 Coln 4
0
1
2
3
4
5
6
7
COLN 3
ROW 10
Bit 2 WEN — This bit enables the background Window 2
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 2 with two extra color
selections, making a total of four selections for that row.
Bit 0 VPOL — This bit selects the polarity of the incoming
vertical sync signal (VFLB) on Pin 5. If it is negative polarity,
clear this bit. Otherwise, set this bit to 1 to represent the posi-
tive V sync signal. After power–on, this bit is cleared.
COL START ADDR
COLN 4
0
1
2
3
4
5
6
7
ROW 10
VPOL
Row 10 Coln 5
Bit 2–0 R, G and B — These bits control the color of Win-
dow 2. Window 1 occupies Columns 0–2 of Row 10; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
R
G
COL END ADDR
COLN 5
0
1
2
3
4
5
6
7
B
ROW 10
Window 3 Registers
Row 10 Coln 6
0
1
2
3
4
5
6
7
COLN 6
ROW 10
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