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MC143421
MOTOROLA
3
Table 1. Pin Descriptions
Pin No.
Signal Name
I/O Type
Function
1
C/BE[3]#
I
PCI Bus Command and Byte Enable
2
IDSEL
I
PCI Initialization Device Select; Chip Select for Configuration Read and Write Cycles
3
GND
Ground
4
VCC
AD[23]
Power 5 V
5
I/O
PCI Bus Multiplexed Address and Data
6
AD[22]
I/O
PCI Bus Multiplexed Address and Data
7
AD[21]
I/O
PCI Bus Multiplexed Address and Data
8
AD[20]
I/O
PCI Bus Multiplexed Address and Data
9
GND
Ground
10
AD[19]
I/O
PCI Bus Multiplexed Address and Data
11
AD[18]
I/O
PCI Bus Multiplexed Address and Data
12
AD[17]
I/O
PCI Bus Multiplexed Address and Data
13
AD[16]
I/O
PCI Bus Multiplexed Address and Data
14
VCC
GND
Power 5 V
15
Ground
16
C/BE[2]#
I
PCI Bus Command and Byte Enable
17
FRAME#
I
PCI Cycle Frame; Indicates the Beginning and Duration of a Bus Access
18
IRDY#
I
PCI Initiator Ready; Indicates the Bus Master’s Ability to Complete the Current Data Phase of
the Transaction
19
GND
Ground
20
TRDY#
O
PCI Target Ready; Indicates the Target Agent’s Ability to Complete the Current Data Phase of
the Transaction
21
DEVSEL#
O
PCI Device Select for Configuration Read and Write Cycles
22
STOP#
O
PCI Stop; Indicates the Current Target Request for Transceiver Termination
23
PAR
O
Indicates Even Parity Across AD[31:0] and C/BE[3:0]#
24
GND
Ground
25
VCC
C/BE[1]#
Power 5 V
26
I
PCI Bus Command and Byte Enable
27
AD[15]
I/O
PCI Bus Multiplexed Address and Data
28
AD[14]
I/O
PCI Bus Multiplexed Address and Data
29
AD[13]
I/O
PCI Bus Multiplexed Address and Data
30
GND
Ground
31
AD[12]
I/O
PCI Bus Multiplexed Address and Data
32
AD[11]
I/O
PCI Bus Multiplexed Address and Data
33
AD[10]
I/O
PCI Bus Multiplexed Address and Data
34
AD[9]
I/O
PCI Bus Multiplexed Address and Data
35
GND
Ground
36
AD[8]
I/O
PCI Bus Multiplexed Address and Data
37
C/BE[0]#
I
PCI Bus Command and Byte Enable
38
AD[7]
I/O
PCI Bus Multiplexed Address and Data
39
AD[6]
I/O
PCI Bus Multiplexed Address and Data
40
GND
Ground
41
VCC
AD[5]
Power 5 V
42
I/O
PCI Bus Multiplexed Address and Data