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參數(shù)資料
| 型號： | MC143421FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Interface |
| 中文描述： | PCI BUS CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 189K |
| 代理商： | MC143421FU |
MC143421
MOTOROLA
7
Table 2. PCI Configuration Space Description
Please reference PCI Specification 2.1 and “Addition of PME# Signal to Connector” ECN.
Offset
Bits
Type
Description
Value
00h
15:0
RO
Vendor ID
1057h
02h
31:16
RO
Device ID
3421h
04h
29
RO
Master Abort
28
RO
Target Abort
26:25
RO
Medium Device
2100000h
20
RO
New Capabilities (ACPI)
2
RO
Master Enable
1
RW
Memory Enable
0
RW
I/O Enable
08h
31:8
RO
PCI Multimedia Device
048000h
7:0
RO
Revision ID
00h
0ch
23:16
RO
Header Type
0h
15:8
RO
Latency Timer
10h
31:8
RW
256–Byte I/O Space
7:1
RO
I/O Size
0h
0
RO
I/O Space Indicator
1b
14h
31:12
RW
4K Memory Space
11:1
RO
Memory Size
0h
0
RO
Memory Space Indicator
0b
2ch
31:20
RO
Subsystem ID
0h
19:16
RO
Subsystem ID
From ha[3:0]
During Reset
15:8
RO
Subvendor ID
0h
7:0
RO
Subvendor ID
From hd[7:0]
During Reset
34h
7:0
RO
Cap_Ptr (ACPI)
40h
3ch
15:11
RO
Interrupt Pin
0h
10:8
RO
INTA#
1b
7:0
RW
Interrupt Line
40h
31:0
RO
PMC (ACPI)
6c210001h
44h
15
RW
PEN_status — This bit is set when the function would normally assert the
PME# signal independent of the state of the PME_En bit. Writing a 1 to
this bit will clear it and cause the function to stop asserting a PME# (if
enabled). Writing a 0 has no effect.
8
RW
PEN_EN — A 1 enables the function to assert PME#. When 0, PME#
assertion is disabled.
1:0
RW
PowerState — This two–bit field is used both to determine the current
power state of the function and to set the function into a new power state.
The definition of the field values is given below:
00b
D0
01b
D1
10b
D2
11b
D3hot
NOTES:
1. RO: Read Only Register
2. RW: Read and Write Register
3. All other registers not shown in the table will return 0s.
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