參數(shù)資料
型號: MC145173
廠商: Motorola, Inc.
元件分類: 通用總線功能
英文描述: Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter
中文描述: 雙頻鎖相環(huán)頻率合成器ADC和頻率計數(shù)器
文件頁數(shù): 15/33頁
文件大?。?/td> 277K
代理商: MC145173
MC145173
15
MOTOROLA
Table 3. VHF PDout Response
N Register
Bit
R Register Bits
VHF Phase Detector Response (Nominal)
N15
R18
R17
L
L
L
Linear response, no low–gain region
L
L
H
Low–gain region, 5 ns wide
L
H
L
Low–gain region, 10 ns wide
L
H
H
Low–gain region, 15 ns wide
H
L
L
Linear response, no dead zone
H
L
H
Dead zone, 5 ns wide
H
H
L
Dead zone, 10 ns wide
H
H
H
Dead zone, 15 ns wide
NOTES:
1. L = Low Level, H = High Level.
2. See Figure 19.
NOTES:
1. Output HF PDout always has a linear transfer characteristic. Therefore, for HF PDout, the Dead Zone = 0 ns.
2. Output VHF PDout has a response which is programmable via bits
φ
det1 (R18),
φ
det0 (R17), and Zone (N15).
See Table 3.
3. The gain in the “l(fā)ow–gain region” is reduced to 7% of the gain in the other region.
DEAD ZONE
OR
LOW–GAIN REGION
LOW–PASS FILTER
OUTPUT VOLTAGE
LINEAR
RESPONSE
LOW
GAIN
REGION
PHASE ERROR
NONLINEAR RESPONSES
Figure 19. VHF PDout Transfer Characteristic
Table 4. Test Modes
R Register Bits
Pin Configurations
R21
R18
R17
Pin 12 — OUTPUT A
Pin 13 — OUTPUT B
L
L
L
OUTPUT A, normal configuration
OUTPUT B, normal configuration
L
L
H
fV, N counter output — HFin feeds the counter input
fV, N counter output — VHFin feeds the counter input
OUTPUT A, normal configuration
OUTPUT B, normal configuration
L
H
L
OUTPUT B, normal configuration
L
H
H
fR, R counter output
OUTPUT B, normal configuration
H
X
X
OUTPUT A, normal configuration
NOTE: L = Low Level, H = High Level, X = Don’t Care.
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