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參數(shù)資料
| 型號： | MC145193 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1.1GHz PLL Frequency Synthesizer(1.1GHz PLL頻率合成器) |
| 中文描述： | 1.1GHz的鎖相環(huán)頻率合成器（1.1GHz的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 269K |
| 代理商： | MC145193 |
MC145193
5
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85
°
C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)
Parameter
Figure
No.
Symbol
Guaranteed
Limit
Unit
Serial Data Clock Frequency (Note: Refer to Clock tw below)
Maximum Propagation Delay, CLK to Output A (Selected as Data Out)
1
fclk
dc to 4.0
MHz
1, 5
tPLH, tPHL
tPLH, tPHL
tPZL, tPLZ
tTLH, tTHL
Cin
100
ns
Maximum Propagation Delay, ENB to Output A (Selected as Port)
2, 5
150
ns
Maximum Propagation Delay, ENB to Output B
2, 6
150
ns
Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B
Maximum Input Capacitance – Din, ENB, CLK
1, 5, 6
50
ns
10
pF
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85
°
C, Input tr = tf = 10 ns, unless otherwise indicated)
Parameter
Figure
No.
Symbol
Guaranteed
Limit
Unit
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold and Recovery Times, ENB vs CLK
3
tsu, th
tsu, th, trec
tw
tw
tr, tf
50
ns
4
100
ns
Minimum Pulse Width, ENB
4
[Note]
cycles
Minimum Pulse Width, CLK
1
125
ns
Maximum Input Rise and Fall Times, CLK
1
100
μ
s
NOTE:
The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
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