參數(shù)資料
型號(hào)： MC145230
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 1/71頁(yè)
文件大?。?/td> 906K
代理商： MC145230
SEMICONDUCTOR
TECHNICAL DATA
BiCMOS COMPONENT
FOR 2 OR 3 VOLT
SYSTEMS
PLASTIC PACKAGE
CASE 873C
(LQFP–32, Tape & Reel Only)
VERY–SMALL 5 x 5 mm BODY
32
1
Order this document by MC145225/D
DEVELOPMENT SYSTEM
The MC145230EVK, which contains hardware and
software, is strongly recommended for system
development. (The user must provide the VCOs for
evaluating the MC145181.) The software supports
all features and modes of operation of the device. Up
to four boards or devices can be controlled and the
user is alerted to error conditions. The control
program may be used with any board based on the
MC145181, MC145225, or MC145230.
Device
Main/Secondary
Loop
Maximum
Frequency
Package
ORDERING INFORMATION
LQFP–32
MC145225FTAR2
MC145230FTAR2
2200/550 MHz
1200/550 MHz
(Scale 2:1)
1
"
"# !
The MC145225 and MC145230 are dual frequency synthesizers
containing very–low supply voltage circuitry. These devices support two
independent loops with a single input reference and operate down to 1.8 V.
Phase noise reduction circuitry is incorporated into each device.
The MC145225 is capable of direct usage up to 1.2 GHz on the main loop
and up to 550 MHz on the secondary loop. The MC145230 is capable of
direct usage up to 2.2 GHz on the main loop and up to 550 MHz on the
secondary loop. Each device has a 32/33 prescaler for the main loop and an
8/9 prescaler for the secondary loop. Lock detection circuitry for each loop is
multiplexed to a single output.
Two 8–bit DACs are powered through a dedicated pin. The DAC supply
range is 1.8 to 3.6 V; this voltage may differ from the main supply.
An on–chip voltage multiplier supplies power to the phase/frequency
detectors. Thus, in a 2 V application, the detectors are supplied with 4 V
power. In 2.6 to 3.6 V applications, the multiplied voltage is regulated at
approximately 5 V. The current source/sink phase/frequency detector for the
main loop is designed to achieve faster lock times than a conventional
detector. Both high and low current outputs are available along with a timer,
double buffers, and a MOSFET switch to adjust the external low–pass filter
response.
There are several levels of standby which are controllable with a 1–byte
transfer through the serial port. Either of the PLLs and/or the reference
oscillator may be independently placed in the low–power standby state. In
addition, any of the phase/frequency detector outputs may be placed in the
floating state to facilitate modulation of the external VCOs. Either DAC may
be placed in standby via a 4–byte transfer.
Operating Frequency
MC145225 — Main Loop: 100 to 1200 MHz
Secondary Loop: 50 to 550 MHz
MC145230 — Main Loop: 500 to 2200 MHz
Secondary Loop: 50 to 550 MHz
Operating Supply Voltage: 1.8 to 3.6 V
Nominal Supply Current, Both Loops Active — MC145225: 4 mA
MC145230: 5 mA
Maximum Standby Current, All Systems Shut Down: 10
μ
A
Nominal Phase Detector Output Current:
1.8 V Supply — PDout–Hi: 2.8 mA, PDout–Lo: 0.7 mA
2.5 V Supply — PDout–Hi: 4.4 mA, PDout–Lo: 1.1 mA
Two Independent 8–Bit DACs with Separate Supply Pin (Up to 3.6 V)
Lock Detect Output with Adjustable Lock Indication Window
Independent R Counters Allow Independent Step Sizes for Each Loop
Main Loop Divider Range: 992 to 262,143
Secondary Loop Divider Range: 152 to 65,535
Fractional Reference Counters Divider Range: 20 to 32,767.5
Auxiliary Reference Divider with Small–Signal Differential
Output — Ratios: 8, 10, 12.5
Three General–Purpose Outputs
Direct Interface to Motorola SPI Data Port Up to 10 Mbps
BitGrabber is a trademark of Motorola, Inc.
Motorola, Inc. 1999
Rev 1
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
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