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參數(shù)資料
| 型號： | MC14549BCPG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTER 8BIT APPROX 16-DIP |
| 標準包裝： | 500 |
| 系列： | 4000B |
| 邏輯類型： | 逐次近似寄存器 |
| 輸出類型： | 標準 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 功能： | 通用 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-DIP |
| 包裝： | 管件 |
MC14549B, MC14559B
http://onsemi.com
5
OPERATING CHARACTERISTICS
Both the MC14549B and MC14559B can be operated in
either the “free run” or “strobed operation” mode for
conversion schemes with any number of bits. Reliable
cascading and/or recirculating operation can be achieved if
the End of Convert (EOC) output is used as the controlling
function, since with EOC = 0 (and with SC = 1 for
MC14549B but either 1 or 0 for MC14559B) no stable state
exists under continual clocked operation. The MC14559B
will automatically recirculate after EOC = 1 during externally
strobed operation, provided SC = 1.
All data and control inputs for these devices are triggered
into the circuit on the positive edge of the clock pulse.
Operation of the various terminals is as follows:
C = Clock — A positivegoing transition of the Clock is
required for data on any input to be strobed into the circuit.
SC = Start Convert — A conversion sequence is initiated
on the positivegoing transition of the SC input on
succeeding clock cycles.
D = Data in — Data on this input (usually from a
comparator in A/D applications) is also entered into the
circuit on a positivegoing transition of the clock. This input
is Schmitt triggered and synchronized to allow fast response
and guaranteed quality of serial and parallel data.
MR = Master Reset (MC14549B Only) — Resets all
output to 0 on positivegoing transitions of the clock. If
removed while SC = 0, the circuit will remain reset until
SC = 1. This allows easy cascading of circuits.
FF = Feed Forward (MC14559B Only) — Provides
register shortening by removing unwanted bits from a system.
For operation with less than 8 bits, tie the output following
the least significant bit of the circuit to EOC. E.g., for a 6bit
conversion, tie Q1 to FF; the part will respond as shown in the
timing diagram less two bit times. Not that Q1 and Q0 will
still operate and must be disregarded.
For 8bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16 bits, use
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly to
the least significant bit used in the MC14559B allows EOC
to provide the cascading signal, and results in smooth
transition of serial information from the MC14559B to the
MC14549B. The Serial Out (Sout) inhibit structure of the
MC14559B remains inactive one cycle after EOC goes high,
while Sout of the MC14549B remains inhibited until the
second clock cycle of its operation.
Qn = Data Outputs — After a conversion is initiated the
Q’s on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once
conditionally reset they remain in the proper state until the
circuit is either reset or reinitiated.
EOC = End of Convert — This output goes high on the
negativegoing transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can
indicate complete conversion.
Sout = Serial Out — Transmits conversion in serial
fashion. Serial data occurs during the clock period when the
corresponding parallel data bit is conditionally reset. Serial
Out is inhibited on the initial period of a cycle, when the
circuit is reset, and on the second cycle after EOC goes high.
This provides efficient operation when cascaded.
Figure 1. 12Bit Conversion Scheme
Completion of conversion automatically reinitiates cycle in free run mode.
** Cascading using EOC guaranteed; no stable unfunctional state.
* FF allows EOC to activate as if in 4stage register.
Q7 Q6 Q5 Q4
Q0 EOC
FF
SC
C
D
Sout
MC14559B
NC
MSB
TO D/A AND PARALLEL DATA
**
*
FROM A/D
COMPARATOR
Q7 Q6 Q5
MR
SC
C
D
Sout
MC14549B
LSB
Q4 Q3 Q2 Q1 Q0 EOC
TO D/A AND
PARALLEL DATA
{
EXTERNAL STROBE
FREE RUN MODE
EXTERNAL
CLOCK
1/4 MC14001
SERIAL OUT
(CONTINUAL
UPDATE EVERY
13 CLOCK CYCLES)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC14549BDWR2 | 功能描述:寄存器 3-18V SAR RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC14549BDWR2G | 功能描述:寄存器 3-18V SAR RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC145502FNR2 | 制造商:Freescale Semiconductor 功能描述: |
| MC145502P | 制造商:Motorola Inc 功能描述: |
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