參數(shù)資料
型號(hào): MC14LC5004
廠商: Motorola, Inc.
英文描述: Regulating Pulse-Width Modulators 16-SOIC 0 to 70
中文描述: 128段LCD驅(qū)動(dòng)器
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 245K
代理商: MC14LC5004
3–7
MC14LC5003 MC14LC5004
MOTOROLA
The MC14LC5003/MC14LC5004 has essentially two sec-
tions which operate asynchronously from each other; the data
input and storage section and the LCD drive section. The LCD
drive and timing is derived from the oscillator, while the data
input and storage is controlled by the Data In (D
in
), Data Clock
(DCLK), Address (A0, A1, A2), and Enable (ENB) pins.
Data is shifted serially into the 128-bit shift register and ar-
ranged into four consecutive blocks of 32 parallel data bits. A
time-multiplex of the four backplane drivers is made (each
backplane driver becoming active then inactive one after an-
other) and, at the start of each backplane active period, the
corresponding block of 32 bits is made available at the front-
plane drivers. A high input to a plane driver turns the driver
on, and a low input turns the driver off.
Figure 4 shows the sequence of backplanes. Figure 5 shows
the possible configurations of the frontplanes relative to the
backplanes. When a backplane driver is on, its output switches
from V
LCD
to 0 V, and when it is off, it switches from 1/3 V
LCD
to 2/3 V
LCD
. When a frontplane driver is on, its
output switches from 0 V to V
LCD
, and when it is off, it switches
from 2/3 V
LCD
to 1/3 V
LCD
.
The LCD drive and timing section provides the multiplex sig-
nals and backplane driver input signals and formats the front-
plane and backplane waveforms.
The address pins are used to uniquely distinguish LCD driver
from any other chips on the same bus and to define LCD driver
as the “master” in the system. There must be one master in any
system.
The enable pin may be used as a third control line in the
communication bus. It may be used to define the moment
when the data is latched. If not used, then the data is latched
after 128 bits of data have been received.
Figure 4. Backplane Sequence
BP1
V
LCD
2/3 (V
LCD
)
1/3 (V
LCD
)
0 V
TIME FRAME
BP2
V
LCD
2/3 (V
LCD
)
1/3 (V
LCD
)
0 V
BP3
V
LCD
2/3 (V
LCD
)
1/3 (V
LCD
)
0 V
BP4
V
LCD
2/3 (V
LCD
)
1/3 (V
LCD
)
0 V
FUNCTIONAL DESCRIPTION
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