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參數(shù)資料
| 型號： | MC33689DWBR2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | System Basis Chip with LIN transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片收發(fā)器和LIN |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 229K |
| 代理商： | MC33689DWBR2 |
MC33689
14
MC33689
Sleep and stop mode enter:
To safely enter sleep or stop mode and to ensure that these modes are not entered by noise issue during SPI transmission, a
dedicated sequence combining bit controlling the LIN bus and the device mode must be send twice.
Enter sleep mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=0) 11x0_0000 must be
sent.
Enter stop mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=1) 11x0_0001 must be
sent.
Sleep or stop mode is entered after the second SPI command. D5 bit must be set accordingly.
5.9
Window watchdog.
The window watchdog is configurable using external resistor at Wdc pin. The W/D is cleared through mode1 and mode 2 bit is
SPI register. If Wdc pin is left open a fixed watchdog period is selected (typ 150ms). If no watchdog function is required or to
disable the watchdog, the Wdc pin must be connected to gnd. The watchdog period is calculated by the following formula:
Twd = 0.991 * R +0.648 (with R in kohms and Twd in ms).
Watchdog clear:
The watchdog is cleared by SPI write command with following mode1 and mode2 bits.
Normal
Vdd: ON
N/A
- High.
- Active low if Vdd
under voltage occurs
or if W/D fail (if W/D
enable)
Window WD if
enabled.
ON or
OFF
Transmit
and
Receive
Active
Stop
Vdd ON,
limited current
capability
LIN and
state
change on
Lx inputs
- Normally high.
- Active low if Vdd
under voltage occurs
Disable
OFF
Recessive
state with
Wake
capability
Not
active
Sleep
Vdd OFF, (Set
to 5V after
wake up to
enter Normal
request)
LIN and
state
change on
Lx inputs
- Low
- Go to high after wake
up and Vdd within
spec
Disable
OFF
Recessive
state with
Wake
capability
Not
active
Mode 2
Mode 1
Mode
0
Sleep mode (note 1)
01
Stop mode
1
0
Normal mode + W/D clear (note 2)
1
Normal mode
Device
Mode
Voltage
Regulator
Wake up
capabilities
Reset output
Watchdog
function
HS1
HS2
HS3
LIN
interface
Opera-
tional
amplifier
Table 5-1.
window closed
window open
Twd * 50%
Watchdog period
for watchdog clear
no watchdog clear allowed
Twd
Window watchdog operation
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC33696FCAER2 | 功能描述:射頻收發(fā)器 UHF TRANSCEIVER ECHO RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
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