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參數(shù)資料
| 型號： | MC33689DWBR2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | System Basis Chip with LIN transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片收發(fā)器和LIN |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 229K |
| 代理商： | MC33689DWBR2 |
MC33689
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MC33689
Note 1: Special SPI command and sequence is implemented in order to avoid to go into sleep or stop mode with a single 8 bit
SPI command.
Note 2: When a zero is written to “Mode1” bit while “Mode2” bit is written as a one, after the SPI command is completed
“Mode1” bit is set to one and SBC stays in normal mode. In order to set the SBC in sleep mode, both “Mode1” and “Mode2” bits
must be written in the same 8 bits SPI command.
The W/D clear on normal request mode (150ms) has no window.
5.10
INT pin:
This pin is used to report fault to the MCU. Int pulse is generated in case of:
- Vdd regulator temperature pre warning
- high side switch 1, 2 or 3 thermal shutdown
- Vsup over voltage (20V typ)
- Vsup under voltage (6V typ).
If an INT is generated, when the next SPI read operation is performed bit D7 is set to 1. This mean that the bits (D6 to D0)
report the interrupt source.
In case of wake up from stop mode, INT is set low in order to signal to the MCU wake up event from L1, L2 or LIN bus.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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