參數(shù)資料
型號: MC33882
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Six-Output Low-Side Switch with SPI and Parallel Input Control(帶SPI和并口輸入控制的6輸出低端開關)
中文描述: 六輸出低壓側(cè)開關SPI和并行輸入控制(帶的SPI和并口輸入控制的6輸出低端開關)
文件頁數(shù): 11/24頁
文件大小: 779K
代理商: MC33882
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
11
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V
V
DD
5.25 V, 9.0 V
V
PWR
17 V, -40
°
C
T
A
125
°
C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (Note 25)
t
R
1.0
10
μ
s
Output Fall Time (Note 25)
t
F
1.0
10
μ
s
Output Turn-ON Delay Time (Note 26)
t
DLY(ON)
1.0
10
μ
s
Output Turn-OFF Delay Time (Note 27)
t
DLY(OFF)
1.0
10
μ
s
Output Short Fault Sense Time (Note 28)
R
LOAD
= < 1.0 V
t
SS
25
100
μ
s
Output Short Fault Refresh
Time (Note 29)
R
LOAD
= < 1.0 V
t
REF
3.0
4.5
6.0
ms
Output OFF Open Load Sense Time (Note 30)
t
OS(OFF)
25
60
100
μ
s
Output ON Open Load Sense Time (Note 31)
t
OS(ON)
3.0
12
ms
Output Short Fault ON Duty Cycle (Note 32)
SC
DC
0.42
3.22
%
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) (Note 33)
t
SCLKH
141
ns
SCLK Clock Low Time (SCLK = 3.2 MHz) (Note 33)
t
SCLKL
141
ns
Falling Edge (0.8 V) of
CS
to Rising Edge (2.0 V) of SCLK
Required Setup Time (Note 33)
t
LEAD
140
ns
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of
CS
Required Setup Time (Note 33)
t
LAG
50
ns
SI,
CS
, SCLK Incoming Signal Rise Time (Note 33)
t
RSI
50
ns
SI,
CS
, SCLK Incoming Signal Fall Time (Note 33)
t
FSI
50
ns
Notes
25.
Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15
resistive load to a V
BAT
of
15 V, V
PWR
= 15 V.
Output Turn-ON Delay Time measured from rising edge (3.0 V) V
IN
(
CS
for serial) to 90% V
O
using a 15
load to a V
BAT
of 15 V,
V
PWR
= 15 V.
Output Turn-OFF Delay Time measured from falling edge (1.0 V) V
IN
(3.0 V rising edge of
CS
for serial) to 10% V
O
using a 15
load to a
V
BAT
of 15 V, V
PWR
= 15 V.
The shorted output is turned ON during t
SS
to retry and check if the short has cleared. The shorted output is in current limit during t
SS
. The
t
SS
is measured from the start of current limit to the end of current limit.
The Short Fault Refresh Time is the waiting period between t
SS
retry signals. The shorted output is disabled during this refresh time. The
t
REF
is measured from the end of current limit to the start of current limit.
The t
OS(OFF)
is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of
CS
must occur at least 100
μ
s after the faulted output is off.
The t
OS(ON)
is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault register.
To guarantee a fault is reported on SO, the falling edge of
CS
must occur at least 12 ms after the faulted output is ON.
Percent Output Short Fault ON Duty Cycle is defined as (t
SS
)
÷
(t
REF
) x 100. This specification item is provided FYI and is not tested.
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
26.
27.
28.
29.
30.
31.
32.
33.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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