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參數(shù)資料
| 型號： | MC33882 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Six-Output Low-Side Switch with SPI and Parallel Input Control(帶SPI和并口輸入控制的6輸出低端開關(guān)) |
| 中文描述： | 六輸出低壓側(cè)開關(guān)SPI和并行輸入控制（帶的SPI和并口輸入控制的6輸出低端開關(guān)） |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 779K |
| 代理商： | MC33882 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
17
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33882 incorporates six 1.0 A low-side switches using
both Serial Peripheral Interface (SPI) I/O as well as optional
parallel input control to each output. There are also two low-
power (30 mA) low-side switches with SPI diagnostic feedback,
but parallel-only input control. The 33882 incorporates
SMARTMOS technology with CMOS logic, bipolar/MOS
analog circuitry, and DMOS power MOSFETs. Designed to
interface directly with a microcontroller, it controls inductive or
incandescent loads. Each output is configured as an open drain
transistor with dynamic clamping.
FUNCTIONAL TERMINAL DESCRIPTION
V
PWR
Terminal
The V
PWR
terminal is connected to battery voltage. This
supply is provided for overvoltage shutdown protection and for
added gate drive capabilities. A decoupling capacitor is
required from V
PWR
to ground.
IN0 & IN1, IN2 & IN3, and IN4 & IN5 Terminals
These input terminals control two output channels each
when the
MODE
terminal is pulled high: IN0 & IN1 controls
OUT0 and OUT1, IN2 & IN3 controls OUT2 and OUT3, while
IN4 & IN5 controls OUT4 and OUT5. These terminals may be
connected to PWM outputs of the control IC and pulled high or
pulled low to control output channel states while the
MODE
terminal is high. The states of these terminals are ignored
during normal operation (
MODE
terminal low) and override the
normal inputs (serial or parallel) when the
MODE
terminal is
high. These terminals have internal active 25
μ
A pull-downs.
MODE
Terminal
The
MODE
terminal is connected to the
MODE
terminal of the
control IC. This terminal has an internal active 25
μ
A pull-up.
When pulled high, the
MODE
terminal does the following:
Disables all serial control of the outputs while still reading
any serial input commands.
Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5
control of the outputs.
Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input
terminals for control of OUT0 and OUT1, OUT2 and
OUT3, OUT4 and OUT5, respectively.
Turns off OUT6 and OUT7.
Tri-states the SO terminal.
IN0 to IN7 Terminals
These are parallel input terminals connected to output
terminals of the control IC. Each parallel input is logic high with
the corresponding SPI control bit to control each output
channel. These terminals have internal 25
μ
A active pull-
downs.
OUT0 to OUT7 Terminals
Each terminal is one channel's low-side switch output. OUT0
to OUT5 are actively clamped to handle inductive loads.
SI Terminal
The Serial Input terminal is connected to the SPI Serial Data
Output terminal of the control IC from where it receives output
command data. This input has an internal active 25
μ
A pull-
down and requires CMOS logic levels. The serial data
transmitted on this line is an 8- or 16-bit control command sent
MSB first, controlling the six output channels. Bits A5 through
A0 control channels 5 through 0, respectively. Bits A6 and A7
enable ON open load fault detection on channels 5 through 0.
The control IC will ensure that data is available on the rising
edge of SCLK. Each channel has its serial control bit high with
its parallel input to determine its state.
SCLK Terminal
The SCLK terminal of the control IC is a bit (shift) clock for
the SPI port. It transitions one time per bit transferred when in
operation. It is idle between command transfers. It is 50% duty
cycle and has CMOS levels. This signal is used to shift data to
and from the device. For proper fault reporting operation, the
SCLK input must be low when
CS
transitions from high to low.
CS
Terminal
The
CS
terminal is connected to a chip select output of the
control IC. The control IC controls which device is addressed by
pulling the
CS
terminal of the desired device low, enabling the
SPI communication with the device, while other devices on the
serial link keep their serial outputs tri-stated. This input has an
internal active 25
μ
A pull-up and requires CMOS logic levels.
SO Terminal
The Serial Output terminal is connected to the SPI Serial
Data Input terminal of the control IC or to the SI terminal of the
next device in a daisy chain. This output will remain tri-stated
unless the device is selected by a low
CS
terminal or the
MODE
terminal goes low. The output signal generated will have CMOS
logic levels and the output data will transition on the falling
edges of SCLK. The serial output data provides fault
information for each output and is returned MSB first when the
device is addressed. Fault bit assignments for return data are
as follows: MSB-0 through MSB-7 are output fault bits for OUT7
to OUT0, respectively. In 8-bit SPI mode, under normal
conditions, the SO terminal (not daisy chained) returns all 0s,
representing no faults. If a fault is present, a 1 is returned for the
appropriate bit. In 16-bit SPI mode, sending a double command
byte will provide a command verification byte following the fault
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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