參數(shù)資料
型號(hào)： MC33972
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Multiple Switch Detection Interface with Suppressed Wake-Up(帶抑制喚醒功能的多開(kāi)關(guān)檢測(cè)接口)
中文描述： 多交換檢測(cè)接口，具有抑制喚醒（帶抑制喚醒功能的多開(kāi)關(guān)檢測(cè)接口）
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 819K
代理商： MC33972
33972/D
14
Go to: www.freescale.com
Wetting Current Timer Register
Each switch input has a designated 20 ms timer. The timer
starts when the specific switch input crosses the comparator
threshold (4.0 V). When the 20 ms timer expires, the contact
current is reduced from 16 mA to 2.0 mA. The wetting current
timer may be disabled for a specific input. When the timer is
disabled, 16 mA of current will continue to flow through the
closed switch contact. With multiple wetting current timers
disabled, power dissipation for the IC must be considered.
The MCU may change or update the Wetting Current Timer
Register
via software at any time in Normal mode. This allows
the MCU to control the amount of time wetting current is applied
to the switch contact. Programming the wetting current timer bit
to logic [0] will disable the wetting current timer. Programming
the wetting current timer bit to logic [1] will enable the wetting
current timer (refer to
Table 4
).
Tri-State Register
The
tri-state command
is use to set the SPn or SGn input
node as high impedance (refer to
Table 5
). By setting the
Tri-State Register bit to logic [1], the input will be high
impedance regardless of the metallic command setting. The
comparator on each input remains active. This command allows
the use of each input as a comparator with a 4.0 V threshold.
The MCU may change or update the Tri-State Register
via
software at any time in Normal mode.
Table 4. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
X
X
X
X
X
X
X
X
sp7
sp6
sp5
sp4
sp3
sp2
sp1
sp0
0
0
0
0
1
0
0
0
X
X
sg13 sg12 sg11 sg10
sg9
sg8
sg7
sg6
sg5
sg4
sg3
sg2
sg1
sg0
Table 5. Tri-State Command
Tri-State Commands
Command Bits
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
1
X
X
X
X
X
X
X
X
sp7
sp6
sp5
sp4
sp3
sp2
sp1
sp0
0
0
0
0
1
0
1
0
X
X
sg13 sg12 sg11 sg10
sg9
sg8
sg7
sg6
sg5
sg4
sg3
sg2
sg1
sg0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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