參數(shù)資料
型號(hào)： MC33976
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Dual Gauge Driver with Configurable Response Time(帶可設(shè)置響應(yīng)時(shí)間的雙標(biāo)尺驅(qū)動(dòng)器)
中文描述： 雙計(jì)驅(qū)動(dòng)器，可配置的響應(yīng)時(shí)間（帶可設(shè)置響應(yīng)時(shí)間的雙標(biāo)尺驅(qū)動(dòng)器）
文件頁數(shù)： 12/40頁
文件大小： 5332K
代理商： MC33976
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
33976
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
TIMING DESCRIPTION
This section provides a description of the 33976 SPI behavior. To follow the explanations below, refer to
Table 5
and to the
timing diagrams shown in
Figure 6
and
Figure 7
.
Figure 6. Single 16-Bit Word SPI Communication
Figure 7. Multiple 16-Bit Word SPI Communication
DATA INPUT
The Input Shift register captures data at the falling edge of
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (
CS
in a logic [0] state). By
the time the
CS
signal goes to logic [1] again, the contents of
the Input Shift register are transferred to the appropriate
internal register addressed in bits 15:13. The minimum time
CS
should be kept high depends on the internal clock speed,
specified in the
SPI INTERFACE TIMING
(15)
section of the
Static Electrical Characteristics, found on page
6
. It must be
long enough so the internal clock is able to capture the data
from the Input Shift register and transfer it to the internal
registers.
Table 5. Data Transfer Timing
Pin
Description
CS
(1-to-0)
SO pin is enabled.
CS
(0-to-1)
33976 configuration and desired output states are transferred and executed according to the data
in the Shift registers.
SO
Will change state on the rising edge of the SCLK pin signal.
SI
Will accept data on the falling edge of the SCLK pin signal.
CS
SCLK
SI
SO
Output shift register is loaded here.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Note
SO is tri-stated when
CS
is logic [1].
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D2
D1
D0
D15
*
D14
*
D13
*
D4
D3
D2
*
D1
*
D0
*
OD15
OD14
OD13
OD12
OD11
OD2
OD1
OD0
D15
D14
D13
OD4
OD3
D2
D1
D0
Notes
2. D15, D14, D13, ..., and D0 refer to the first 16 bits of data into the 33976.
3. D15
*
, D14
*
, D13
*
, ..., and D0
*
refer to the most recent entry of program data into the 33976.
4. OD15, OD14, OD13, ..., and OD0 refer to the first 16 bits of fault and status data out of the 33976.
1. SO is tri-stated when
CS
is logic [1].
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