參數(shù)資料
型號： MC33976
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Dual Gauge Driver with Configurable Response Time(帶可設置響應時間的雙標尺驅動器)
中文描述： 雙計驅動器，可配置的響應時間（帶可設置響應時間的雙標尺驅動器）
文件頁數(shù)： 8/40頁
文件大小： 5332K
代理商： MC33976
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
33976
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
SPI INTERFACE TIMING
(15)
Recommended Frequency of SPI Operation
f
SPI
–
1.0
2.0
MHz
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
(16)
t
LEAD
–
50
167
ns
Falling Edge of SCLK to Rising Edge of
CS
(Required Setup Time)
(16)
t
LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
(16)
t
S
ISU
–
25
83
ns
Required High State Duration of SCLK (Required Setup Time
(16)
t
W
SCLK
h
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time
(16)
t
W
SCLK
l
–
–
167
ns
Falling Edge of SCLK to SI (Required Hold Time)
(16)
t
SI
(
HOLD)
–
25
83
ns
SO Rise Time
C
L
= 200 pF
t
R
SO
–
25
50
ns
SO Fall Time
C
L
= 200 pF
t
F
SO
–
25
50
ns
SI,
CS
, SCLK, Incoming Signal Rise Time
(17)
t
R
SI
–
–
50
ns
SI,
CS
, SCLK, Incoming Signal Fall Time
(17)
t
F
SI
–
–
50
ns
Falling Edge of
RST
to Rising Edge of
RST
(Required Setup Time)
(16)
t
W
RST
–
–
3.0
μ
s
Rising Edge of
CS
to Falling Edge of
CS
(Required Setup Time)
(16)
,
(18)
t
CS
–
–
5.0
μ
s
Rising Edge of
RST
to Falling Edge of
CS
(Required Setup Time)
(16)
t
EN
–
–
5.0
μ
s
Time from Falling Edge of
CS
to SO Low Impedance
(19)
t
SO(EN)
–
–
145
ns
Time from Rising Edge of
CS
to SO High Impedance
(20)
t
SO(DIS)
–
1.3
4.0
μ
s
Time from Rising Edge of SCLK to SO Data Valid
(21)
0.2 V
DD
≤
SO
≥
0.8 V
DD
, C
L
= 200 pF
t
VALID
–
90
150
ns
Notes
15.
The 33976 shall meet all SPI interface timing requirements specified in
the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device
shall be fully functional for slower clock speeds.
The maximum setup time specified for the 33976 is the minimum time needed from the microcontroller to guarantee correct operation.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.
Time required for output status data to be terminated at SO. 1.0 k
load on SO
Time required for output status data to be available for use at SO. 1.0 k
load on SO.
Time required to obtain valid data out from SO following the rise of SCLK.
16.
17.
18.
19.
20.
21.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V
≤
V
DD
≤
5.25 V, - 40
°
C
≤
T
J
≤
150
°
C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Units
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