參數(shù)資料
型號： MC34920
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 2.8 Ohm(Typ) Quad H-Bridge Motor Driver(2.8歐（典型值）四H橋電機驅動器)
中文描述： 2.8歐姆（典型值）四H橋電機驅動器（2.8歐（典型值）四魔橋電機驅動器）
文件頁數(shù)： 24/28頁
文件大?。?/td> 813K
代理商： MC34920
34920
24
Go to: www.freescale.com
circuit disables the drive outputs by driving both outputs to the
high state until the device temperatures have dropped below
the lower thermal threshold temperature T
J(ENABLE)
, at which
time the drive is re-enabled.
The crossover delay must be controlled to provide sufficient
time for cross-condition suppression. At no time can both the
upper and lower output devices on the same side of the
H-bridge be allowed to conduct simultaneously. Also, following
a turn-on event a blanking period is included to prevent false
turn-offs owing to the initial turn-on current spike, which results
from motor circuit capacitance.
Note
During power-on the DC Motor Driver circuit inhibits its
outputs when V
VB+
is at 4.0 V or greater until
RESET
is
released. Likewise, during power-down of the machine the DC
Motor Driver circuit inhibits its outputs from the point when
RESET
goes low until V
VB+
has dropped below 4.0 V.
RESET
Functionality
The 34920 provides an output,
RESET
, that drives an
external reset signal to the system microprocessor and/or the
system digital logic IC. This signal is an active low logic level
signal that is derived by monitoring the level of the V
CC
terminal.
This output is the equivalent of an open drain- (or open
collector-) type output, with an internal 2.5 k
pull-up to V
CC
.
This output terminal can be driven by other external sources
and therefore the state of
RESET
must be monitored by the
34920.
Note
When
RESET
is asserted either internally or from an
external source, all 34920 motor drive outputs will be in their
inactive states, and the serial input port will be loaded with the
“Reset Value” (refer to
Tables 4
through
7
). The V2 voltage
regulator will be enabled.
During power-up this output asserts a logic low level, and it
monitors the V1 regulator output voltage and detects the point
that it reaches V
V1T+
. The output will then remain low for a delay
of 15 ms to 50 ms before releasing to a high state. A second
case is if V
V1_FB
is at or above V
V1T+
for a period longer than
the delay period of t
DELAY
and V
VB+
is still less than V
VB+T
-
.
In this situation
RESET
will remain low until V
VB+
is greater than
V
VB+T-
, at which point
RESET
will be released immediately and
there will be no delay period. If V
VB+
passes through V
VB+T+
during the t
DELAY
period,
RESET
will remain low until the end of
the t
DELAY
period, which started at the time V
V1_FB
passed
through the V
V1T+
level.
During power-down this output immediately asserts a logic
low at the point when V
V1_FB
drops down to the trip point of
V
V1T
-
. Also, if V
VB+
drops below V
VB+T
-
and V
V1_FB
is still at or
above V
V1T
-
,
RESET
will be pulled low.
RESET
Behavior
The following conditions describe the behavior of the
RESET
circuit.
A Note on Terminology
Assertion of
RESET
is defined as
the
RESET
terminal outputting a logic low voltage, and de-
assertion is when the terminal is pulled up to the V
CC
voltage.
On the power-up condition,
RESET
behaves as follows:
If 1.0 V < V
V1_FB
< V
V1T+
or V
VB+
< V
VB+T+
,
RESET
will be
asserted.
Important
If V
V1_FB
< 1.0 V,
RESET
is undefined.
If
RESET
is asserted owing to V
V1_FB
< V
V1T
-
, then when
V
V1_FB
rises monotonically from below V
V1T
-
to above
V
V1T+
,
RESET
will de-assert after a duration of t
DELAY
.
If
RESET
is asserted owing to V
VB+
< V
VB+T+
and V
V1_FB
≥
V
V1T+
, then when V
VB+
rises to the V
VB+T+
level
RESET
will de-assert with no delay. The only case where a delay
would be seen is if the time period from where V
V1_FB
rises to the V
V1T+
level to the point where V
VB+
rises to the
V
VB+T+
level is less than the t
DELAY
period. Then the delay
in de-asserting
RESET
would be the remaining t
DELAY
time, thereby maintaining the full t
DELAY
period, between
the time when V
V1_FB
reaches V
V1T+
and the de-assertion
of
RESET
, that is required for a reliable system reset.
On the power-down condition,
RESET
behaves as follows:
If
RESET
is not asserted, and the V
V1_FB
voltage
monotonically decreases to a value below the negative-
going threshold of V
V1T
-
and remains below V
V1T
-
for
longer than t
PERSIST
(10
μ
s
to 30
μ
s
),
RESET
will be
asserted.
RESET
will remain asserted while 1.0 V <
V
V1_FB
< V
V1T+
. If V
V1_FB
falls below 1.0 V, the
RESET
signal is undefined.
RESET
will also be asserted when V
VB+
decreases below
the V
VB+T+
level. This will occur even if the V
V1_FB
level is
still above V
V1T
-
.
On the V
V1_FB
glitch condition,
RESET
behaves as follows:
If the V
V1_FB
supply falls below V
V1T
-
and remains there
for less than t
PERSIST
(10
μ
s to 30
μ
s),
RESET
will not be
asserted. However, if the condition lasts longer than
t
PERSIST
,
RESET
will be asserted for a duration of t
DELAY
.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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MC34921 制造商:SPC Multicomp 功能描述:HEADER R/ANGLE 5WAY 制造商:SPC Multicomp 功能描述:HEADER, R/ANGLE, 5WAY 制造商:SPC Multicomp 功能描述:WIRE-BOARD CONNECTOR, RCPT, 5POS, 4.2MM; Series:2266(5566)S; Pitch Spacing:4.2mm; Contact Termination:Through Hole Right Angle; No. of Contacts:5; No. of Rows:1; Connector Mounting:PCB; Gender:Receptacle; Contact Material:Brass ;RoHS Compliant: Yes
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MC34921AER2 功能描述:馬達/運動/點火控制器和驅動器 DUAL PWM DC MOTOR DRIVE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube
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