參數(shù)資料
型號: MC34923
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Full-Bridge PWM Motor Driver(全橋PWM電機(jī)驅(qū)動器)
中文描述: 全橋PWM電動機(jī)驅(qū)動器(全橋脈寬調(diào)制電機(jī)驅(qū)動器)
文件頁數(shù): 11/16頁
文件大?。?/td> 508K
代理商: MC34923
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
34923
11
D14, Enable Logic
Bit D14, in conjunction with the PWM/ENABLE pin,
determines if the output drivers are in the chopped (OFF) or ON
state.
D15, Direction Logic
Bit D15, in conjunction with the DIR pin, determines if the
device is operating in the forward or reverse state.
D16, Divisor SPAN Select
Bit D16, in conjunction with the SPAN pin, determines if V
REF
is divided by 5 or 10.
D17, Internal PWM Mode
Bit D17, in conjunction with the PWMMODE pin, selects
mixed or slow current decay.
D18, Test Mode
Bit D18 low (default) operates the device in normal mode.
D18 is only used for testing purposes. The user should never
change this bit.
D19, Sleep Mode
Bit D19 selects a Sleep mode to minimize power
consumption when not in use. This disables much of the
internal circuitry, including the regulator and charge pump. On
power-up the serial port is initialized to all zeros. Bit D19 should
be programmed high for 1.0 ms before attempting to enable any
output driver.
Serial Port Write Timing Operations
Data is clocked into the shift register on the rising edge of the
CLOCK signal. Normally STROBE will be held high, only
brought low to initiate a write cycle. Refer to
Figure 2, Serial Port
Write Timing
, page 8, for the minimum timing requirements.
V
REG
This internally generated voltage is used to operate the sink-
side outputs. The V
REG
pin should be decoupled with a 0.22
μ
F
capacitor to ground. V
REG
is internally monitored and, in the
case of a fault condition, the outputs of the device are disabled.
Charge Pump
The charge pump is used to generate a gate supply voltage
greater than V
BB
to drive the source-side gates. A 0.22
μ
F
ceramic capacitor should be connected between CP1 and CP2
for pumping purposes. A 0.22
μ
F ceramic capacitor should be
connected between V
B
and V
BB
to act as a reservoir to operate
the high-side devices. The V
B
voltage is internally monitored
and, in the case of a fault condition, the source outputs of the
device are disabled.
Shutdown
In the event of a fault (excessive junction temperature or low
voltage on V
B
or V
REG
), the outputs of the device are disabled
until the fault condition is removed. At power-up, and in the
event of low V
DD
, the Undervoltage Lockout circuit disables the
drivers and resets the data in the serial port to all zeros.
PWM Timer Function
The PWM timer is programmable via the serial port (bits D2–
D10) to provide off-time PWM signals to the control circuitry. In
the mixed current-decay mode, the first portion of the off time
operates in fast decay, until the fast decay time count (serial bits
D7–D10) is reached, followed by slow decay for the rest of the
off-time period (bits D2–D6). If the fast decay time is set longer
than the off time, the device effectively operates in fast decay
mode. Bit D17, in conjunction with PWMMODE, selects mixed
or slow decay.
PWM/
ENABLE
D14
Operating
Mode
0
0
Chopped
1
1
1
0
ON
0
1
State
DIR
D15
DCMA
DCMB
Reverse
0
0
Low
High
1
1
Forward
1
0
High
Low
0
1
Divisor
SPAN
D16
÷
5
1
0
0
1
÷
10
0
0
1
1
PWMMODE
D17
Current
Decay Mode
0
0
Mixed
1
1
1
0
Slow
0
1
D19
Sleep Mode
0
Sleep
1
Normal
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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