Chapter 23 Voltage Regulator (S12VREGL3V3V1)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
819
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
23.3.2.2
Control Register (VREGCTRL)
The VREGCTRL register allows the conguration of the VREG_3V3 low-voltage detect features.
Table 23-3. VREGHTCL Field Descriptions
Field
Description
7, 6
Reserved
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
5
VSEL
Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
See device level specication for connectivity.
0 An internal temperature proportional voltage VHT can be accessed internally if VAE is set.
1 Bandgap reference voltage VBG can be accessed internally if VAE is set.
4
VAE
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specication for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
3
HTEN
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
2
HTDS
High Temperature Detect Status Bit —
This read-only status bit reects the temperature status. Writes have no effect.
0 Temperature TDIE is below level THTID or RPM or Shutdown Mode.
1 Temperature TDIE is above level THTIA and FPM.
1
HTIE
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0
HTIF
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes. This ag can only be cleared by writing a 1. Writing a 0 has no
effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
0x02F1
76543210
R
00000
LVDS
LVIE
LVIF
W
Reset
0
00000
= Unimplemented or Reserved
Figure 23-3. Control Register (VREGCTRL)