參數(shù)資料
型號： MC44460B
廠商： MOTOROLA INC
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE (PIP) CONTROLLER
中文描述： PICTURE-IN-PICTURE IC, PDIP56
封裝： SHRINK, PLASTIC, DIP-56
文件頁數(shù)： 1/16頁
文件大?。?/td> 439K
代理商： MC44460B
SEMICONDUCTOR
TECHNICAL DATA
PICTURE–IN–PICTURE
(PIP) CONTROLLER
B SUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
56
1
Order this document by MC44460/D
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
MC44460B
TJ = –65
°
to +150
°
C
SDIP
1
MOTOROLA ANALOG IC DEVICE DATA
The MC44460 Picture–in–Picture (PIP) controller is a low cost member of
a family of high performance PIP controllers and video signal processors for
television. It is NTSC compatible and contains all the analog signal
processing, control logic and memory necessary to provide for the overlay of
a small picture from a second non synchronized source onto the main picture
of a television. All control and setup of the MC44460 is via a standard two pin
I2C bus interface. The device is fabricated using BICMOS technology. It is
available in a 56–pin shrink dip (SDIP) package.
The main features of the MC44460 are:
Two NTSC CVBS Inputs
Switchable Main and PIP Video Signals
Single NTSC CVBS Output Allows Simple TV Chassis Integration
Two PIP Sizes; 1/16 and 1/9 Screen Area
Freeze Field Feature
Variable PIP Position in 64–X by 64–Y Steps
PIP Border with Programmable Color
Programmable PIP Tint and Saturation Control
Automatic Main to PIP Contrast Balance
Vertical Filter
Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
Minimal RFI Allows Simple Low Cost Application into TV
I2C Bus Control – No External Variable Adjustments Needed
Operates from a Single 5.0 V Supply
Economical 56–Pin Shrink DIP Package
Representative Block Diagram
Decoder Clamp Caps
Filter PLL
This device contains 500,000 active transistors.
Y
V
U
Y U V
Clamp
Input
Switch
Low Pass
Filter
Band Pass
Filter
NTSC
Decoder
PIP
Switch
4X S/C
Osc + PLL
16X S/C
Osc + PLL
Y
U
V
Clamp
NTSC
Encoder
4X S/C
Osc + PLL
Filter
Tracking
6–Bit
ADC
H and V
Timebase
Digital
Logic
I Ref
Memory
8.0 k x 8
DRAM
Tint DAC
Sat DAC
V DAC
Y DAC
3.0 MHz
LPF
3.0 MHz
LPF
3.0 MHz
LPF
33
Y
V
U
40
41
42
51
29
31
32
1
2
3
4
5
10
30
6
54
53
52
47
46
6
6
6
6
6
3
6
Vert
57.28 MHz
90
°
0
°
14.32 MHz
90
°
0
°
36
34
37
49
38
39
7
44
45
M
Video 1
Video 2
Decoder ACC
Main Out
Decoder Xtal
Decoder PLL
16 FSC PLL
Encoder Phase
Encoder ACC
Sync In
H PLL
503 kHz Res
Hin
Vin
SCL
SDA
Reset
Vid 1/2 Sel
Multi Test
Encoder Clamp Caps
Encoder
Xtal
Encoder
PLL
Cur Ref
ADC Mid–Ref
U DAC
28
Sync Out
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Motorola, Inc. 1996
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