參數(shù)資料
型號: MC54-74HC373A
廠商: Motorola, Inc.
英文描述: Octal 3-State Non-Inverting Transparent Latch
中文描述: 八路三態(tài)非反相透明鎖存器
文件頁數(shù): 3/8頁
文件大?。?/td> 202K
代理商: MC54-74HC373A
MC54/74HC373A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Voltages Referenced to GND)
0.1
0.1
25 C
6.0
|Iout|
20
μ
A
Voltage
Unit
V
0.1
125 C
0.1
85 C
0.1
V
Test Conditions
Vin = VIL
Parameter
Symbol
Maximum Low–Level Output
Vin = VIL or VIH
Vin = VCC or GND
Iout = 0
μ
A
2.4 mA
2.0
0.1
|Iout|
3.0
4.5
0.26
0.26
±
5.0
0.33
0.33
0.4
0.4
Current (per Package)
Current
Maximum Quiescent Supply
Speed CMOS Data Book (DL129/D).
Symbol
b l
Parameter
V
25 C
U i
6.0
6.0
6.0
21
80
90
24
125 C
32
36
38
tPHL
(Figures 1 and 5)
3.0
26
110
26
130
tPHL
(Figures 2 and 5)
3.0
26
150
120
30
210
140
Maximum Propagation Delay, Output Enable to Q
2.0
10
150
190
190
33
225
ns
Maximum Propagation Delay, Output Enable to Q
2.0
6.0
15
33
225
38
ns
Maximum Output Transition Time, Any Output
2.0
6.0
10
60
75
13
15
90
ns
Cin
Cout
Maximum Input Capacitance
10
10
pF
Maximum Three–State Output Capacitance
15
15
pF
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
bl d O
Typical @ 25
°
C, VCC = 5.0 V
36
pF
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