參數(shù)資料
型號(hào): MC56F8006MLF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BBC, LQFP-48
文件頁數(shù): 39/106頁
文件大?。?/td> 1215K
代理商: MC56F8006MLF
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
General System Control Information
Freescale Semiconductor
38
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option
Power-saving clock gating for peripherals
Controls the enable/disable functions of large regulator standby mode with write protection capability
Permits selected peripherals to run in stop mode to generate stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls output of internal clock sources to CLKO pin
Four general-purpose software control registers are reset only at power-on
Peripherals stop mode clocking control
6.7
PWM, PDB, PGA, and ADC Connections
The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input.
The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB
pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of
PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006
Peripheral Reference Manual for additional information.
Figure 15. Synchronization of ADC, PDB
TriggerA
Pre-
TriggerA
TriggerB
+
PGA0 Controller
ANA15
ANA9
ANA7
ADHWT
ADCA
Trigger
SSEL[0]
SSEL[1]
ADCA
+
PGA1 Controller
ANB15 ANB8
ANB6
ADHWT
ADCB
Trigger
SSEL[0]
SSEL[1]
ADCB
Pre-
TriggerB
System
Clock
TMR0
TMR1
SW
CMP0
CMP1
CMP2
PWM
EXT
Trigger0
Trigger1
Trigger2
Trigger3
Trigger4
Trigger5
Trigger6
Trigger7
Programmable Delay Block (PDB)
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