參數(shù)資料
型號(hào): MC56F8006MWL
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PDSO28
封裝: 7.50 X 18 MM, ROHS COMPLIANT, MS-013AE, SOIC-28
文件頁數(shù): 22/106頁
文件大?。?/td> 1215K
代理商: MC56F8006MWL
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Signal/Connection Descriptions
Freescale Semiconductor
22
GPIOB3
(MOSI)
(TIN3)
(ANA3 and
ANB3)
(PWM5)
(CMP1_
OUT
11
16
12
24
Input/
Output
Input/
Output
Input/
Output
Input
Output
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
MOSI — Master out/slave in. In master mode, this pin serves as the
data output. In slave mode, this pin serves as the data input.
TIN3 — Dual timer module channel 3 input.
ANA3 and ANB3 — Analog input to channel 3 of ADCA and ADCB.
PWM5 — The PWM channel 5.
CMP1_OUT— Analog comparator 1 output.
When used as an analog input, the signal goes to the ANA3 and
ANB3.
After reset, the default state is GPIOB3.
GPIOB4
(T0)
(CLKO_0)
(MISO)
(SDA)
(RXD)
(ANA0 and
ANB0)
13
19
15
27
Input/
Output
Input/
Output
Input/
Output
Input/Open-
drain
Output
Input
Analog
Input
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
T0 — Dual timer module channel 0 input/output.
CLKO_0 — This is a buffered clock output; the clock source is
selected by clockout select (CLKOSEL) bits in the clock output
select register (CLKOUT) of the SIM.
MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
SDA — The I2C serial data line.
RXD — The SCI receive data input.
ANA0 and ANB0 — Analog input to channel 0 of ADCA and ADCB.
When used as an analog input, the signal goes to the ANA0 and
ANB0.
After reset, the default state is GPIOB4.
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
Signal
Name
28
SOIC
32
LQFP
32
PSDI
P
48
LQFP
Type
State
During
Reset
Signal Description
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