參數(shù)資料
型號: MC56F8013VFAE
廠商: Freescale Semiconductor
文件頁數(shù): 103/126頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
配用: CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
56F8013/56F8011 Data Sheet, Rev. 12
78
Freescale Semiconductor
Figure 6-12 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)
6.3.10.1
Reserved—Bits 15—2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.10.2
Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
ISAL[23:22]
Write
RESET
00000
0
1
Instruction Portion
Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
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