56F8013/56F8011 Data Sheet, Rev. 12
30
Freescale Semiconductor
Table 4-2 Interrupt Vector Table Contents1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
core
P:$00
Reserved for Reset Overlay2
core
P:$02
Reserved for COP Reset Overlay
core
2
3
P:$04
Illegal Instruction
core
3
P:$06
SW Interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
EOnCE Step Counter
core
7
1-3
P:$0E
EOnCE Breakpoint Unit 0
core
8
1-3
P:$10
EOnCE Trace Buffer
core
9
1-3
P:$12
EOnCE Transmit Register Empty
core
10
1-3
P:$14
EOnCE Receive Register Full
core
11
2
P:$16
SW Interrupt 2
core
12
1
P:$18
SW Interrupt 1
core
13
0
P:$1A
SW Interrupt 0
14
Reserved
15
Reserved
PS
16
0-2
P:$20
Power Sense
OCCS
17
0-2
P:$22
PLL Lock, Loss of Clock Reference Interrupt
FM
18
0-2
P:$24
FM Access Error Interrupt
FM
19
0-2
P:$26
FM Command Complete
FM
20
0-2
P:$28
FM Command, data and address Buffers Empty
21
Reserved
GPIOD
22
0-2
P:$2C
GPIOD
GPIOC
23
0-2
P:$2E
GPIOC
GPIOB
24
0-2
P:$30
GPIOB
GPIOA
25
0-2
P:$32
GPIOA
SPI
26
0-2
P:$34
SPI Receiver Full / Error
SPI
27
0-2
SPI Transmitter Empty
SCI
28
0-2
P:$38
SCI Transmitter Empty
SCI
29
0-2
P:$3A
SCI Transmitter Idle
SCI
30
0-2
P:$3C
SCI Reserved
SCI
31
0-2
P:$3E
SCI Receiver Error
SCI
32
0-2
P:$40
SCI Receiver Full
33, 34
Reserved
I2C
35
0-2
P:$46
I2C
Timer
36
0-2
P:$48
Timer Channel 0
Timer
37
0-2
P:$4A
Timer Channel 1
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