- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67964 > MC56F8025VLD (FREESCALE SEMICONDUCTOR INC) 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | MC56F8025VLD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44 |
| 文件頁數(shù)： | 17/161頁 |
| 文件大?。?/td> | 2160K |
| 代理商： | MC56F8025VLD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁
Flash Access Lock and Unlock Mechanisms
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
113
security mode is enabled, the 56F8025 will disable the core EOnCE debug capabilities. Normal program
execution is otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
There are several methods that effectively lock or unlock the on-chip flash.
7.2.1
Disabling EOnCE Access
On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE
port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active
and provides the chip’s boundary scan capability and access to the ID register, but proper implementation
of flash security will block any attempt to access the internal flash memory via the EOnCE port when
security is enabled.
7.2.2
Flash Lockout Recovery Using JTAG
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash
contents, including the configuration field, thus disabling security (the protection register is cleared). This
does not compromise security, as the entire contents of the user’s secured code stored in flash are erased
before security is disabled on the device on the next reset or power-up sequence.
To
start
the
lockout
recovery
sequence
via
JTAG,
the
JTAG
public
instruction
(LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register.
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer
to the 56F802x and 56F803x Peripheral Reference Manual for more details, or contact Freescale.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
and device to return to normal unsecured operation. Power-on reset will reset both too.
7.2.3
Flash Lockout Recovery using CodeWarrior
CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by
Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory
configuration file. The command “Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same
task as using the Debug menu.
This lockout recovery mechanism is the complete erasure of the internal flash contents, including the
configuration field, thus disabling security (the protection register is cleared).
7.2.4
Flash Lockout Recovery without mass erase
A user can un-secure a secured device by programming the word $0000 into program memory location
$00 7FF7. After completing the programming, both the JTAG TAP controller and the device must be reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC56F8025MLD | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44 |
| MC56F8155VFGE | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| MC56F8355VFGE | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| MC56F8355MFGE | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| MC56F8157VPY | 16-BIT, 120 MHz, OTHER DSP, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8025VLDR | 制造商:Freescale Semiconductor 功能描述:16-BIT DSC, 56800E CORE, 32KB FLASH, 32MHZ, QFP 44 - Tape and Reel 制造商:Freescale Semiconductor 功能描述:IC DSC 16BIT 32KB FLASH 44LQFP 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC |
| MC56F8027 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8027MLH | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT DSPHC 32KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MC56F8027VLD | 制造商:Freescale Semiconductor 功能描述: |
| MC56F8027VLH | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT DSPHC 32KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。