參數(shù)資料
型號: MC56F8123
廠商: Motorola, Inc.
英文描述: 16-bit Hybrid Controllers
中文描述: 16位混合控制器
文件頁數(shù): 19/140頁
文件大?。?/td> 1981K
代理商: MC56F8123
Phase Locked Loop Timing
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
115
Preliminary
10.6 Phase Locked Loop Timing
10.7 Crystal Oscillator Parameters
Table 10-14 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8MHz input crystal.
fosc
48
8
MHz
PLL output frequency2 (fOUT)—56F8323
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
fop
160
260
MHz
PLL output frequency2 (fOUT)—56F8123
fop
160
160
MHz
PLL stabilization time3 -40
° to +125°C
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
tplls
—1
10
ms
Table 10-15 Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal Start-up time
TCS
4510
ms
Resonator Start-up time
TRS
0.1
0.18
1
ms
Crystal ESR
RESR
120
ohms
Crystal Peak-to-Peak Jitter
TD
70
250
ps
Crystal Min-Max Period Variation
TPV
0.12
1.5
ns
Resonator Peak-to-Peak Jitter
TRJ
300
ps
Resonator Min-Max Period Variation
TRP
300
ps
Bias Current, high-drive mode
IBIASH
250
290
A
Bias Current, low-drive mode
IBIASL
80
110
A
Quiescent Current, power-down mode
IPD
—0
1
A
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