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參數(shù)資料
| 型號(hào)： | MC56F8155VFGE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-128 |
| 文件頁(yè)數(shù)： | 74/172頁(yè) |
| 文件大小： | 844K |
| 代理商： | MC56F8155VFGE |
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Power Distribution and I/O Ring Implementation
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
165
Preliminary
Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum capacitor
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8355/56F8155. This chip
contains two internal power regulators. One of them is powered from the VDDA_OSC_PLL pin and cannot
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the VDD_IO pins and provides power to all of the internal digital logic of the core, all
peripherals and the internal memories. This regulator can be turned off, if an external VDD_CORE voltage
is externally applied to the VCAP pins.
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
Flash, RAM and internal logic are powered from the core regulator output
VPP1 and VPP2 are not connected in the customer system
All circuitry, analog and digital, shares a common VSS bus
Figure 12-1 Power Management
REG
CORE
VCAP
I/O
ADC
VDD
VSS
REG
VDDA_OSC_PLL
OSC
VSSA_ADC
VDDA_ADC
VREFH
VREFP
VREFMID
VREFN
VREFLO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC56F8355VFGE | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| MC56F8355MFGE | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| MC56F8157VPY | 16-BIT, 120 MHz, OTHER DSP, PQFP160 |
| MC56F8157VPYE | 16-BIT, 120 MHz, OTHER DSP, PQFP160 |
| MC56F8357VPY60 | 16-BIT, 120 MHz, OTHER DSP, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8156 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8156VFV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述: |
| MC56F8156VFVE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8157 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-BIT HYBRID CONTROLLERS |
| MC56F8157VPY | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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