參數資料
型號: MC56F8155VFGE
廠商: Freescale Semiconductor
文件頁數: 12/172頁
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 128-LQFP
標準包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數: 49
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數據轉換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 128-LQFP
包裝: 托盤
Register Descriptions
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
109
Preliminary
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2
Software Reset (SWR)—Bit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST
bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing
a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)—Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
External Reset (EXTR)—Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On
Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position
will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external
RESET pin being asserted low.
6.5.2.5
Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared
only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the
bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On
Reset.
6.5.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
O
0
SWR
COPR
EXTR
POR
0
Write
RESET
0
00
0
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