參數(shù)資料
型號： MC56F8256VLF
廠商： Freescale Semiconductor
文件頁數(shù)： 10/88頁
文件大小： 0K
描述： DSC 64K FLASH 60MHZ 48-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 39
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Signal/Connection Descriptions
Freescale Semiconductor
18
3.3
MC56F825x/MC56F824x Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses and
as italic, must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and the SIM module’s GPIO
peripheral select (GPSx) registers.
Table 5. MC56F825x/MC56F824x Signal and Package Information
Signal
Name
44
LQFP
48
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
VDD
29
Supply
I/O Power — This pin supplies 3.3 V power to the chip I/O interface.
VDD
29
32
44
VDD
40
44
60
VSS
20
22
30
Supply
I/O Ground — These pins provide ground for chip I/O interface.
VSS
28
31
43
VSS
41
45
61
VDDA
13
15
22
Supply
Analog Power — This pin supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power supply.
VSSA
14
16
23
Supply
Analog Ground — This pin supplies an analog ground to the analog
modules. It must be connected to a clean power supply.
VCAP
17
19
26
Supply
VCAP — Connect a bypass capacitor of 2.2 F or greater between
this pin and VSS to stabilize the core voltage regulator output
required for proper device operation. See Section 8.2, “Electrical
VCAP
39
43
57
TDI
(GPIOD0)
44
48
64
Input
Input/
Output
Input,
internal
pullup
enabled
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDI.
TDO
(GPIOD1)
42
46
62
Output
Input/
Output
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDO.
TCK
(GPIOD2)
111
Input
Input/
Output
Input,
internal
pullup
enabled
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TCK
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