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General System Control Information
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
39
Figure 11. Connecting an External Clock Signal Using GPIO
5.5
Interrupt Controller
The MC56F825x/MC56F824x interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). When an
interrupt of sufficient priority exists, the INTC signals to the 56800E core and provides the address to which to jump to service
the interrupt.
The interrupt controller contains registers that allow each of the 66 interrupt sources to be set to one of three priority levels
(excluding certain interrupt sources that have fixed priority) or to be disabled. Next, all interrupt requests of a given level are
priority encoded to determine the lowest numeric value of the active interrupt requests for that level. Within a given priority
level, the lowest vector number is the highest priority, and the highest vector number is the lowest priority.
Any two interrupt sources can be assigned to faster interrupts. Fast interrupts are described in the DSP56800E Reference
Manual. The interrupt controller recognizes fast interrupts before the core does.
A fast interrupt is defined by:
1. Setting the priority of the interrupt as level 2 with the appropriate field in the Interrupt Priority Register (IPR)
registers
2. Setting the Fast Interrupt Match (FIMn) register to the appropriate vector number
3. Setting the Fast Interrupt Vector Address Low (FIVALn) and Fast Interrupt Vector Address High (FIVAHn)
registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is
a level 2 interrupt, the INTC handles it as a Fast Interrupt. The INTC takes the vector address from the appropriate FIVALn and
FIVAHn registers, instead of generating an address that is an offset from the VBA.
The core then fetches the instruction from the indicated vector address instead of jumping to the vector table. If the instruction
is not a JSR, the core starts its fast interrupt handling. Refer to section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual
for details.
Table 48 on page 85 provides the MC56F825x/MC56F824x’s interrupt table contents and interrupt priority structure.
5.6
System Integration Module (SIM)
The SIM module consists of the glue logic that ties together the system-on-a-chip. It controls distribution of resets and clocks
and provides a number of control features, including pin muxing control, inter-module connection control (such as connecting
comparator output to eFlexPWM fault input), individual peripheral enabling/disabling, clock rate control for quad timers and
SCIs, enabling peripheral operation in stop mode, and port configuration overwrite protection. For more information, refer to
the device’s reference manual.
The SIM is responsible for the following functions:
Chip reset sequencing
Core and peripheral clock control and distribution
Stop/wait mode control
System status control
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
CLKIN
External Clock (
≤ 120 MHz)
EXT_SEL & CLK_MODE = 1
GPIOC_PER0 = 0
GPS_C0 = 1
MC56F825x/MC56F824x
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