參數資料
型號: MC56F8323VFB60
廠商: Freescale Semiconductor
文件頁數: 106/140頁
文件大?。?/td> 0K
描述: IC MPU HYBRID DSP 32K 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數: 27
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 12K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數據轉換器: A/D 8x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
56F8323 Technical Data, Rev. 17
68
Freescale Semiconductor
Preliminary
5.6.5.6
GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.7
GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6
Interrupt Priority Register 5 (IPR5)
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.2
SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Base + $5
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
SCI1_RCV
IPL
SCI1_RERR
IPL
0
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
Write
RESET
0
000
0
0000000
0
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