Reserved—B" />
參數(shù)資料
型號: MC56F8323VFB60
廠商: Freescale Semiconductor
文件頁數(shù): 121/140頁
文件大小: 0K
描述: IC MPU HYBRID DSP 32K 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 27
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 12K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Register Descriptions
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
81
Preliminary
5.6.24
Reserved—Base + 17
5.6.25
Reserved—Base + 18
5.6.26
Reserved—Base + 19
5.6.27
Reserved—Base + 1A
5.6.28
Reserved—Base + 1B
5.6.29
Reserved—Base + 1C
5.6.30
ITCN Control Register (ICTL)
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1
Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3
Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Base + $1D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
INT
IPIC
VAB
INT_DIS
1
0
IRQA STATE
0
IRQA
EDG
Write
RESET
0
10
000
00
0
1
0
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