參數(shù)資料
型號： MC56F8323VFBE
廠商： Freescale Semiconductor
文件頁數(shù)： 132/140頁
文件大小： 0K
描述： IC MPU HYBRID DSP 32K 64-LQFP
標準包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，SCI，SPI
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 27
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 12K x 8
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Register Descriptions
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
91
Preliminary
6.5.7.4
INDEX0 (INDEX)—Bit 7
0 = Peripheral output function of GPIOB[5] is defined to be INDEX0
1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK
6.5.7.5
HOME0 (HOME)—Bit 6
0 = Peripheral output function of GPIOB[4] is defined to be HOME0
1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure 3-4)
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
00000 = SYS_CLK (from ROCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = MSTR_OSC Oscillator output
01000 = Fout (from OCCS)
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
6.5.8
SIM GPIO Peripheral Select Register (SIM_GPS)
All of the peripheral pins on the 56F8323 and 56F8123 share their I/O with GPIO ports. To select
peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI 1, Quad Timer C and
SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO
functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral
has control. The default peripherals are SPI 0, Quad Timer C, and PWMA.
Note: PWM is NOT available in the 56F8123 device.
As shown in Figure 6-10, the GPIO has the final control over the pin function. SIM_GPS simply decides
which peripheral will be routed to the I/O.
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