- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1948 > MC56F8323VFBE (Freescale Semiconductor)IC MPU HYBRID DSP 32K 64-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MC56F8323VFBE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 138/140頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU HYBRID DSP 32K 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 60MHz |
| 連通性： | CAN，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 27 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 12K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.25 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
| 配用： | MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁當(dāng)前第138頁第139頁第140頁
Clock Generation Overview
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
97
Preliminary
6.5.10.2
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal
oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler
can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks
to be disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip Clock
Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details.
The memory, peripheral and core clocks all operate at the same frequency (60MHz max).
6.7 Power-Down Modes
The 56F8323/56F8123 operate in one of three power-down modes, as shown in Table 6-2
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK =
60MHz.
Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system
frequency, which can be controlled through the OCCS.
Table 6-2 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Active
Device is fully functional
Wait
Core and memory
clocks disabled
Active
Peripherals are active and can produce
interrupts if they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
The only possible recoveries from Stop mode
are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts (IRQA)
3. COP reset
4. External reset
5. Power-on reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC56F8335VFGE | IC DIGITAL SIGNAL CTLR 128-LQFP |
| MC56F8345MFGE | IC DSP 16BIT 60MHZ 128-LQFP |
| MC56F8346VFVE | IC DSP 16BIT 60MHZ 144-LQFP |
| MC56F8366VFVE | IC DSP 16BIT 60MHZ 144-LQFP |
| MC68020RC33E | IC MICROPROCESSOR 32BIT 114-PGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8335 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller |
| MC56F8335E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller |
| MC56F8335MFG60 | 制造商:Freescale Semiconductor 功能描述:16 BIT HYBRID CONTROLLER - Trays |
| MC56F8335MFGE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8335VFG60 | 制造商:Freescale Semiconductor 功能描述:16 BIT HYBRID CONTROLLER - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。