參數(shù)資料
型號(hào): MC56F8346
廠商: Motorola, Inc.
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 56F8346 16位混合控制器
文件頁數(shù): 132/160頁
文件大?。?/td> 1415K
代理商: MC56F8346
132
56F8346 Technical Data
Preliminary
10.6 External Clock Operation Timing
Figure 10-3 External Clock Timing
10.7 Phase Locked Loop Timing
Table 10-13 External Clock Operation Timing Requirements
1
1.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
2
2.
See
Figure 10-3
for details on using the recommended connection of an external clock driver.
f
osc
0
120
MHz
Clock Pulse Width
3
3.
The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
t
PW
3.0
ns
External clock input rise time
4
4.
External clock input rise time is measured from 10% to 90%.
t
rise
10
ns
External clock input fall time
5
5.
External clock input fall time is measured from 90% to 10%.
t
fall
10
ns
Table 10-14 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
correctly. The PLL is optimized for 8MHz input crystal.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
f
osc
4
8
8
MHz
PLL output frequency
2
(f
OUT
)
2.
56F8300 Peripheral User Manual
.
ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
OUT
/2), please refer to the OCCS chapter in the
f
op
160
260
MHz
PLL stabilization time
3
-40
°
to +125
°
C
3.
This is the minimum time required after the PLL set up is changed to ensure reliable operation.
t
plls
1
10
ms
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
t
fall
t
rise
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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