參數資料
型號： MC56F8347VVFE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PBGA160
封裝： ROHS COMPLIANT, MAPBGA-160
文件頁數： 105/172頁
文件大?。?/td> 2620K
代理商： MC56F8347VVFE
56F8347 Technical Data, Rev.11
38
Freescale Semiconductor
Preliminary
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the
specific OCCS block diagram to reference in the OCCS chapter of the 56F8300 Peripheral User Manual.
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
MUX
EXTAL
XTAL
FEE
D
BACK
LCK
Prescaler CLK
Postscaler CLK
FOUT/2
Crystal
OSC
Loss of
Reference
Clock
Detector
Lock
Detector
ZSRC
Bus Interface & Control
FOUT
F
REF
PLLDB
PLLCOD
PLLCID
Bus
Interface
Loss of Reference
Clock Interrupt
SYS_CLK2
Source to SIM
MUX
CLKMODE
÷2
Prescaler
÷ (1,2,4,8)
Postscaler
÷ (1,2,4,8)
MS
T
R
_OS
C
PLL
x (1 to 128)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC56F8147VVFE,MC56F8347VVFE
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相關代理商/技術參數
參數描述
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