參數(shù)資料
型號： MC56F8347VVFE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PBGA160
封裝： ROHS COMPLIANT, MAPBGA-160
文件頁數(shù)： 56/172頁
文件大?。?/td> 2620K
代理商： MC56F8347VVFE
Controller Area Network (CAN) Timing
56F8347 Technical Data, Rev.11
Freescale Semiconductor
149
Preliminary
10.14 Controller Area Network (CAN) Timing
Note: CAN is not available in the 56F8147 device.
Figure 10-18 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-22 CAN Timing1
1. Parameters listed are guaranteed by design
Characteristic
Symbol
Min
Max
Unit
See Figure
Baud Rate
BRCAN
—
1
Mbps
—
Bus Wake Up detection
T WAKEUP
5
—
μs
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
TCK frequency of operation using EOnCE 1
1. TCK frequency of operation must be less than 1/8 the processor rate.
fOP
DC
SYS_CLK/8
MHz
TCK frequency of operation not using EOnCE1
fOP
DC
SYS_CLK/4
MHz
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data set-up time
tDS
5—
ns
TMS, TDI data hold time
tDH
5—
ns
TCK low to TDO data valid
tDV
—30
ns
TCK low to TDO tri-state
tTS
—30
ns
TRST assertion time
tTRST
2T2
2. T = processor clock period (nominally 1/60MHz)
—ns
T WAKEUP
CAN_RX
CAN receive
data pin
(Input)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC56F8147VVFE,MC56F8347VVFE
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