參數(shù)資料
型號(hào)： MC56F8355MFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝： ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數(shù)： 144/172頁
文件大?。?/td> 844K
代理商： MC56F8355MFGE
Features
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
73
Preliminary
5.2 Features
The ITCN module design includes these distinctive features:
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-5, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
1. Core status register bits indicating current interrupt mask within the core.
SR[8]1
Permitted Exceptions
Masked Exceptions
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2, 3
Priorities 0, 1
1
Priority 3
Priorities 0, 1, 2
Table 5-2 Interrupt Priority Encoding
IPIC_LEVEL[1:0]1
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No Interrupt or SWILP
Priorities 0, 1, 2, 3
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PDF描述
MC56F8157VPY 16-BIT, 120 MHz, OTHER DSP, PQFP160
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8355VFG60 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Hybrid Controllers
MC56F8355VFGE 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8356 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F8356 16-bit Hybrid Controller
MC56F8356MFV60 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC56F8356MFVE 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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