參數(shù)資料
型號: MC56F8355VFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數(shù): 47/172頁
文件大?。?/td> 844K
代理商: MC56F8355VFGE
56F8355 Technical Data, Rev. 17
140
Freescale Semiconductor
Preliminary
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 10-3 Signal States
10.4 Flash Memory Characteristics
10.5 External Clock Operation Timing
Table 10-12 Flash Timing Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Program time1
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual
for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro-
gram Flash module, as it contains two interleaved memories.
Tprog
20
μs
Erase time2
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
Terase
20
ms
Mass erase time
Tme
100
ms
Table 10-13 External Clock Operation Timing Requirements1
1. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
2. See Figure 10-4 for details on using the recommended connection of an external clock driver.
fosc
0—
120
MHz
Clock Pulse Width3
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
tPW
3.0
ns
External clock input rise time4
4. External clock input rise time is measured from 10% to 90%.
trise
10
ns
External clock input fall time5
5. External clock input fall time is measured from 90% to 10%.
tfall
10
ns
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
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