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| 型號(hào)： | MC68150FN33 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 36/40頁(yè) |
| 文件大?。?/td> | 631K |
| 代理商： | MC68150FN33 |
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MC68150
5
MOTOROLA
High Performance Frequency
Control Products — BR1334
Table 2. 68150 TRUTH TABLE (WRITE Mode)
SIZ1
SIZ0
PA1
PA0
DSACK1
DSACK0
D31:24
D23:16
D15:8
D7:0
PD31:24
PD23:16
Description of Transfer
Fig
L
H
L
In0
X
Out0
X
8-Bit WRITE to 32-Bit Peripheral
50
L
H
L
H
L
X
In1
X
Out1
52
L
H
L
X
In2
X
54
L
H
L
X
In3
X
56
L
H
L
H
In0
X
Out0
X
8-Bit WRITE to 16-Bit Peripheral
42
L
H
L
H
L
H
X
In1
X
Out1
44
L
H
L
H
X
In2
X
Out2
X
46
L
H
L
H
X
In3
X
Out3
48
L
H
L
H
L
In0
X
Out0
X
8-Bit WRITE to 8-Bit Peripheral
34
L
H
L
H
L
X
In1
X
Out1
X
36
L
H
L
H
L
X
In2
X
Out2
X
38
L
H
L
X
In3
Out3
X
40
H
L
X
L
In0
In1
X
Out0
Out1
16-Bit WRITE to 32-Bit Peripheral
30
H
L
H
X
L
X
In2
In3
X
32
H
L
X
L
H
In0
In1
X
Out0
Out1
16-Bit WRITE to 16-Bit Peripheral
26
H
L
H
X
L
H
X
In2
In3
Out2
Out3
28
H
L
H
L
In0
In1
X
Out0
X
16-Bit WRITE to 8-Bit Peripheral
22
H
L
H
L
.
X
Out1
X
(2 Transfers)
H
L
H
L
H
L
X
In2
In3
Out2
X
16-Bit WRITE to 8-Bit Peripheral
24
H
L
H
L
X
.
Out3
X
(2 Transfers)
LL or HH
X
L
In0
In1
In2
In3
Out0
Out1
32-Bit WRITE to 32-Bit Peripheral
18
LL or HH
L
X
L
H
In0
In1
In2
In3
Out0
Out1
32-Bit WRITE to 16-Bit Peripheral
16
LL or HH
H
X
L
H
.
Out2
Out3
(2 Transfers)
LL or HH
L
H
L
In0
In1
In2
In3
Out0
X
32-Bit WRITE to 8-Bit Peripheral
14
LL or HH
L
H
L
.
Out1
X
(4 Transfers)
LL or HH
H
L
H
L
.
Out2
X
LL or HH
H
L
.
Out3
X
X = Don’t Care (Do Not Leave Inputs Floating);
. = Latched Data From Processor; Z = 3-State; InX = Input (0 Signifies the MSB and 3 Signifies
the LSB); OutX = Output Corresponding to the Input InX
TYPICAL SYSTEM CONFIGURATION
A 68040 system using the MC68150 for dynamic bus sizing consists minimally of the MC68040 microprocessor, the
MC68150, a PAL for timing control, and various size memory devices. When a 32-bit port is required, two F245’s must be used
to buffer the PD15–PD0 bits to the D15–D0 bits of the ‘040, since the MC68150 does not support these bits. The typical system
configuration (Figure 2) illustrates communication between a 68040 and 8-, 16-, and 32-bit peripheral chips.
Design Guidelines
Peripheral data connections are the same as for a 68030
– Connect PD31:24 for 8-bit port
– Connect PD31:24 for upper byte 16-bit port
– Connect PD23:16 for lower byte 16-bit port
– Connect PD31:24 for upper-upper byte 32-bit port
– Connect PD23:16 for upper-middle byte 32-bit port
– Connect PD15:8 for lower-middle byte 32-bit port
– Connect PD7:0 for lower-lower byte 32-bit port
32-bit ports require transceivers or latched transceivers for PD15:0
– The MC68150 only passes the upper 16 data bits on a 32-bit transfer
68150 does not support burst mode
– One way to handle this is to connect TA of the 68150 to TBI of the 68040
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68150
32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
NETCOM
IDT 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC68150
5
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