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參數(shù)資料
| 型號： | MC68150FN33 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 384K |
| 代理商： | MC68150FN33 |
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MC68150
6
MOTOROLA
High Performance Frequency
Control Products — BR1334
2. MC68040 BUS OPERATION
An access is divided into multiple states. Each state represents half a clock period. All even states are defined when BCLK
is High, all odd states are defined when BCLK is low. A clock edge is referenced by the state that follows the clock edge. All rising
edges are referenced by even number states. All falling edges are referenced by odd number states. DS0 is the first state of an
access. DSW represents a wait state or a mid-access transfer state. A wait state indicates an access is occurring, but that the
MC68150 is waiting on the peripheral to complete the transaction. Note that the peripheral and MPU states are distinct, though
related, to each other. The peripheral states start with S0. Figure 4 is an example transfer with the states marked.
2.1 Access Start
The MC68040 begins an access by asserting the transfer control signals and transfer start (TS). The transfer control signals
are held by the MC68040 throughout the access. The transfer start is asserted around only one rising edge of the clock (BCLK).
The chip select (CS) for the MC68150 is asserted while the MC68040 transfer control signals are input to the MC68150.
The transfer control signals (A1, A0, SIZ1, SIZ0, R/W) must all be valid a set-up time before the rising edge of BCLK on which
CS recognized (DS2). If the transfer control signals change states during this set-up time, the MC68150 operation is unpredictable.
The transfer control signals must be held valid until at least DS4. If the CS switches during the set-up time before the rising edge
of DS2, then the access may not be recognized until the next clock edge. Once asserted, CS must be held asserted until the end
of the access.
During a write access, the data signals (D(31:0)) must be valid a set-up time before the rising edge of DS2. The ‘040 data is
latched into the 68150 off the DS2 rising clock edge (as long as CS is recognized as described above). This latched data is internally
held by the 68150 until CS is negated at the end of a transfer.
Figure 4. MC68150 32-Bit to 8-Bit Transfer Example (READ or WRITE)
UWE, LWE,
SWE
S14
DS10
DSW
DS8
DS7
DS9
DS6
DS5
S18
S17
S16
S15
S13
S12
S11
S10
S9
S8
DSW
DS3
DS2
DSW
DS4
DS1
DS0
S7
S6
S5
S4
S3
S2
S1
S0
= Driven but undefined.
DSACK1,
DSACK0
DS
PD(31:24)
[READ]
PA(1:0)
PD(31:24)
[WRITE]
TA
D(16:0)
[READ]
D(31:16)
[READ]
D(31:0)
[WRITE]
Transfer Controls = A1, A0, SIZ1, SIZ0 and R/W
TRANSFER
CONTROLS
CS
BCLK
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