參數(shù)資料
型號(hào)： MC68150FN33
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 38/40頁(yè)
文件大?。?/td> 384K
代理商： MC68150FN33
MC68150
7
MOTOROLA
High Performance Frequency
Control Products — BR1334
2.2 Early Access Termination
An access through an MC68150 can be terminated before completion by negating CS early. The CS negation is recognized
on a rising edge of BCLK. The CS early negation is used when the access should be ignored, such as when a bus error occurs.
Any data transferred through the MC68150 is lost when an early access negation occurs. If the access must be completed at a
later time, the entire access must be repeated. To guarantee that TA is not asserted during early negation, CS must be negated
before DS6.
For peripherals that can be read or written to twice, special care must be taken in aborting the 68150 access.
2.3 Early Release of the MPU Bus
Though early MPU bus release is not economical for most applications, it may allow an incremental improvement in
performance at the expense of additional logic.
The transfer control signals (A1, A0, SIZ1, SIZ0, R/W) are held valid at least until DS4. During a write access, the data signals
are held valid at least until DS4. After this hold time, the transfer control signals may change without affecting operation as long
as CS remains asserted. This allows the MC68150 to release the MPU bus before the access is complete on the peripheral side
of the MC68150. During a read access, early release is of limited use, because the MC68040 will not be able to use the bus until
the peripheral data has been read. On a write, early MPU bus release does allow the MC68040 to continue with the next operation
while the MC68150 completes the access.
When using this early release feature, a bus error could be difficult to handle. If the peripheral asserts a bus error after the
MC68040 receives a TA, meaning the transfer is complete, then a subsequent bus error assertion to the MC68040 will not match
the offending address with the bus error address. This can be handled by software or hardware that reads a bit to see if the bus
error is coming from the MC68150.
Another consideration in using early bus release is the handling of back to back transfers and transfer acknowledges. The
chip select logic for the MC68150 must recognize when a second access occurs while completing an access on the peripheral
side. The CS must be negated for one rising edge of BCLK between accesses. The transfer acknowledge from the MC68150
signals the end of the access. If early bus release is used, then the transfer acknowledge generated by the MC68150 should not
be sent to the MC68040.
R/W
DSACK0
DSACK1
DS
PD(23:16)
[READ]
PA(1:0)
PD(31:24)
[READ]
TA
D(16:0)
[READ]
D(31:16)
[READ]
TRANSFER
CONTROLS
CS
BCLK
UWE, LWE,
SWE
DS11
DS10
10
00
DS9
ACCESS
END
SECOND
TRANSFER
FIRST TRANSFER
ACCESS
START
DS8
DS7
DS6
DS5
S9
S8
DSW
DS3
DS2
DSW
DS4
DS1
DS0
S7
S6
S5
S4
S3
S2
S1
S0
Figure 5. 32-Bit ‘040 READ from 16-Bit Peripheral With Asynchronous Termination
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