參數資料
型號： MC68160BFB
廠商： MOTOROLA INC
元件分類： 網絡接口
英文描述： ENHANCED ETHERNET INTERFACE TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP52
封裝： PLASTIC, LQFP-52
文件頁數： 18/30頁
文件大小： 372K
代理商： MC68160BFB
MC68160 MC68160B MC68160C
18
MOTOROLA ANALOG IC DEVICE DATA
TP TRANSMIT SWITCHING
Characteristic
Symbol
Min
Typ
Max
Unit
TPTX Common Mode AC Output Voltage (Note 3)
VOCMTP
t130
t131
t132
–
–
50
mVrms
TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24)
Bit Duration Center–to–Center
Half–Bit Cell Duration Center–to–Boundary
–
98
48
–
–
–
200
102
52
ns
TENA Assert to RENA Assert Delay (Note 7) (See Figure 24)
t133
–
–
400
ns
Internal Loopback Delay from TX to RX (Note 7) (See Figure 24)
(MC68160, MC68160C)
(MC68160B)
t134
t134
–
–
–
–
450
650
ns
TPTX End of Packet Hold Time from last positive TPTX Signal Edge to
+585 mV Differential Output Level (Note 5) (See Figure 25)
t135
250
–
400
ns
TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25)
(MC68160, MC68160C)
(MC68160B)
t136
t136
–
–
45–58
38–58
–
–
ns
RENA Deassert Delay from TENA Deassert when Receiver is inactive
Motorola Mode (MC68160, MC68160C)
Motorola Mode (MC68160B)
Fujitsu Mode (MC68160 Only)
National Mode (MC68160 Only)
Intel Mode (Note 4) (See Figure 26) (MC68160 Only)
t137
t137
t137
t137
t138
250
250
250
250
250
–
–
–
–
–
450
500
450
450
450
ns
TPTX Data–to–Link Test Pulse (Note 2) (See Figure 27)
TPTX Link Test Pulse Width (Note 2)
TPTX Link Test Pulse Decay–to–Idle Condition (Note 1)
TPTX Link Test Pulse to next Link Test Pulse (Note 2)
t139
t140
t141
t142
8.0
80
80
8.0
–
–
–
–
24
240
240
24
ms
ns
ns
ms
NOTES:
1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/– pins of the device.
2. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/– pins of the device.
3. Measured across the output of Test Load C which is connected directly to the TPTX+/– pins of the device.
4. Same as t137 except the logic states for TENA and RENA are inverted.
5. Measured across the output of Test Load B shown in Figure 21.
6. Measured at the +/–90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.)
7. Load on specified output is 20 pF to ground.
100
μ
H
Device
39
39
1.0
μ
H
1.0
μ
H
100pF
100pF
VOUT
100
39
39
100
200
μ
H
39
39
47.5
47.5
49.9
VCM
200
μ
H
39
39
100
VOUT
NOTE:
A total of 50
per driver output is required for proper series line termination.
This is realized with the 39
external resistors shown in Figures 20 to 23,
together with the internal driver output resistance.
Vout
Figure 20. Test Load A
Figure 21. Test Load B
Figure 22. Test Load C
Figure 23. Test Load D
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相關代理商/技術參數
參數描述
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